Multi-level Methodology for CMOS SOI/SOS MOSFET Parameterization for IC Radiation Hardness Simulation with SPICE
The multi-level methodology for CMOS SOI/SOS IC element parameterization for VLSI radiation hardness prediction by CAD systems is developed. The methodology includes semiconductor technology simulation, CMOS SOI/SOS MOSFET device simulation with radiation effects, irradiated test structures investigation, radiation dependent SPICE model parameter extraction with ICCAP. The measured data of irradiated MOSFET test structures is used for TCAD calibration and SPICE model creation. The results show a good correlation between the simulated with the developed models and measured IC and VLSI response to the total dose and other components of the radiation environment.