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November 10, 2026
Physicists Train AI to Optimise Particle Beams in Accelerators
Researchers from the AI and Digital Science Institute at the HSE Faculty of Computer Science and the Budker Institute of Nuclear Physics at the Siberian Branch of the Russian Academy of Sciences have developed RLABC (Reinforcement Learning for Accelerator Beamline Control), a framework that uses reinforcement learning to identify optimal settings for a particle accelerator. In a computer simulation, RLABC optimised the accelerator's parameters to achieve a particle transmission rate of 70%. The study has been published in Computer Physics Communications.
November 9, 2026
'Organ-on-a-Chip Technology Could Eliminate the Need for Animal Testing'
The Laboratory of Molecular Physiology at the HSE Faculty of Biology and Biotechnology investigates how molecular regulators known as microRNAs control gene expression and contribute to the development of diseases, including cancer, viral and inflammatory conditions, and pregnancy complications. At HSE University, researchers develop organ-on-a-chip models: miniature devices containing living cells that mimic the functions of human organs, such as the placenta and intestines. These models help researchers understand how diseases develop and how drugs affect them. HSE News Service spoke with Evgeny Knyazev, Head of the Laboratory.
November 9, 2026
Flattened Terrain Models Underestimate Vehicle-to-Vehicle Communication Outages
Researchers at HSE MIEM have shown that widely used simulators of vehicle-to-vehicle communication significantly overestimate its reliability because they assume flat terrain. When terrain features, bridges, and tunnels are taken into account, the outage rate on a mountain serpentine road rises from 21% to 30%, on an overpass from 20% to 33%, and in a tunnel from 0% to 80%. The results have been published in Future Transportation.

 

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Методы преобразования параллелизма в процессе высокоуровневого синтеза СБИС

Моделирование и анализ информационных систем. 2022. Т. 29. № 1. С. 60–72.
Рыженко И. Н., Непомнящий О. В., Legalov A., Шайдуров В. В.

In this paper methods for increasing the efficiency of VLSI development based on the method of architecture-independent design are proposed. The route of high-level VLSI synthesis is considered. The principle of constructing a VLSI hardware model based on the functional-flow programming paradigm is stated.
The results of the development of methods and algorithms for transformation functional-parallel programs into programs in HDL languages that support the design process of digital chips are presented. The principles of assessment are considered and the classes of resources required for the analysis of design solutions are identified. Reduction coefficients and methods of their calculation for each resource class have been introduced. An algorithm for calculating the reduction coefficients and estimating the required resources is proposed. An algorithm for converting parallelism is proposed, taking into account the specified constraints of the target platform. A mechanism for the exchange of metrics with an architecture-dependent level has been developed. Examples of parallelism reduction for the FPGA platform and practical implementation of FFT algorithms in the Virtex® UltraScale FPGA basis are given. The developed methods and algorithms make it possible to use the method of architecture-independent synthesis for transferring VLSI projects to various architectures by changing the parallelism of the circuit and equivalent transformations of parallel programs. The proposed approach provides many options for hardware solutions for implementation on various target platforms.

Research target: Computer Science
Language: Russian
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Keywords: VLSIdataflowпараллельные вычисленияparallel computingfunctional programmingВысокоуровневый синтезфункционально-потоковое параллельное программированиеhigh-level synthesisпотоки данныхцифровая интегральная схема
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