Implementation of the RISC-V Architecture with the Extended Zbb Instruction Set

P. 180–184.

Markov D., Romanov A.

RISC-V is a new and rapidly developing instruction set architecture, the main feature of which is its openness for the free use. For this reason, RISC-V is becoming more and more popular among companies with a wide range of specializations, both with hardware and software developers. The RISC-V architecture specification defines a set of standard extensions in addition to the basic instruction set architecture that can be useful in a variety of applications among which is the use in automation and process control systems in Electrical power engineering. One of the useful extensions is an extension for bit manipulation, whose instructions were originally invented by Intel and ARM in order to improve power consumption and performance. This work presents an implementation of the Zbb extension of basic bit manipulation in the Verilog language. The developed module is integrated into the schoolRISCV soft processor core. Its modeling and verification of correct operation were carried out using the ModelSim software. The processor was synthesized and prototyped on the Terasic DE1-SoC FPGA board. In addition, support for new instructions from the implemented extension was added to the assembler. Runtime simulator RARS was used also. The analysis of the performance of the extended core showed an average acceleration of the program execution by 29.9%; the amount of memory occupied was reduced by 37.5%. The increase in performance was achieved due to the consumption of a larger number of logic elements and registers.

Keywords: FPGA, RISC-V, ISA, microarchitecture

Publication based on the results of: Research of new promising topologies and routing methods for use in networks-on-сhip (2022)

In book

2022 International Ural Conference on Electrical Power Engineering (UralCon)

IEEE, 2022.