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Digital Filtering Algorithms for Signal Processing in NoCs
P. 225–230.
This paper discusses the application of networks-on-chip (NoCs) for solving DSP problems. NoC is a promising architecture for organizing multicore DSP systems due to scalability and parallel data transfer between IP-cores. Filtering was chosen as a task for signal processing in this work. A technique for partitioning the filtering task into multiple network nodes. An HDL model of the DSP system was created in which the NoC is organized in a circulant topology. The speech signal sampling filtering experiment was conducted using an FPGA based development board.
Mikhail Y. Romashikhin, Aleksandr Y. Romanov, IEEE Access 2026 Vol. 14 P. 7921–7931
This paper presents a hardware-software multi-FPGA complex designed for hardware prototyping of networks-on-chip (NoCs). The rationale for the use of multiple FPGAs for NoC prototyping is given. The architecture of the complex and its components–the software part generating top-level files and configuration files describing the NoC for several FPGAs, hardware part consisting of interfacing switches ...
Added: January 22, 2026
Mazen Makhlouf, Elezov M., Ozhegov R. et al., , in: Proceedings of the 2025 7th International Youth Conference on Radio Electronics, Electrical and Power Engineering (REEPE).: United States of America: IEEE, 2025. P. 1–5.
High-resolution photon-counting optical time-domain reflectometry (PC-OTDR) is crucial for the development of fiber-optic sensing and network diagnostics, allowing accurate fault location and long-haul performance optimization. A major step forward for OTDR is reported by combining a superconducting nanowire single-photon detector (SNSPD) with a low-cost FPGA-based time-to-digital converter (TDC) to perform high-resolution measurements over 150 km ...
Added: January 12, 2026
Romanova I., Amerikanov A., Romanov A., М.: ДМК Пресс, 2025.
Программируемые логические интегральные схемы (ПЛИС, FPGA) составляют основу современных цифровых систем и широко используются на всех этапах их внедрения – начиная
от проведения экспериментальных исследований до разработки и создания конкретного
оборудования. ПЛИС широко применяются в системах обработки аудио- и видеосигналов,
системах обработки сетевого трафика, ускорителях вычислений и т. д. Поэтому подготовка
специалистов, которые могут эффективно применять ПЛИС во всех ...
Added: January 8, 2026
Volkov V., Romanova I., , in: 2025 International Russian Automation Conference (RusAutoCon).: IEEE, 2025. P. 461–466.
Added: October 5, 2025
Смит С., М.: ДМК Пресс, 2025.
Данная книга продолжает серию «Книжная полка Истового инженера»,
которая издается при поддержке компании YADRO. Издание подготовлено к
публикации Московским институтом электроники и математики им. А. Н. Тихонова НИУ ВШЭ совместно с издательством «ДМК Пресс».
Перед вами переведенная и адаптированная для русскоязычного читателя книга С. Смита «RISC-V Assembly Language Programming», вышедшая
в издательстве Apress в серии Maker Innovations в 2024 ...
Added: May 25, 2025
M. Y. Romashikhin, I. I. Romanova, , in: 2024 International Conference on Industrial Engineering, Applications and Manufacturing (ICIEAM), 20-24 May 2024.: IEEE, 2024. P. 996–1000.
The paper provides an overview of the current state of research in the field of combinational circuits reliability and parameters. Architecture of OpenLane flow, its components and main stages of work are described. Based on this flow, the main parameters are provided that will be used for augmentation and expansion of combinational circuits dataset and ...
Added: October 12, 2024
Gorshkov A., Rumyantsev K., Yakovlev P., Working papers by Cornell University. Series math "arxiv.org" 2024
Handling vast amounts of data is crucial in today's world. The growth of high-performance computing has created a need for parallelization, particularly in the area of machine learning algorithms such as ANN (Approximate Nearest Neighbors). To improve the speed of these algorithms, it is important to optimize them for specific processor architectures. RISC-V (Reduced Instruction ...
Added: October 8, 2024
Popov M., Romanov A., Lecture Notes in Networks and Systems 2024 Vol. 1013 P. 341–350
The article considers a combined hard and software method for generation of a high-determined control sequence of pulses for stepper and servo motors to perform multi-axis actuator’s positioning which is typical for CNC equipment. Simulation in MATLAB/Simulink IDE is performed to predict possible distortion of control sequence in a case of pulse generation for two ...
Added: August 18, 2024
Popov M., Shishova M., Romanov A., , in: 2023 International Ural Conference on Electrical Power Engineering (UralCon).: Magnitogorsk: IEEE, 2023. P. 200–204.
Development of a high-speed data transfer subsystem to connect a computer and an external equipment is very relevant for a wide variety of areas - industry, medicine, scientific research and many others. At first glance, modern high-speed interfaces provide all the possibilities to complete the task. In practice, developers face a number of difficulties that ...
Added: June 14, 2024
Magnitogorsk: IEEE, 2023.
Added: June 14, 2024
Mikhail Romashikhin, Romanov A., , in: 2023 International Russian Automation Conference (RusAutoCon) 10-16 Sept. 2023.: Sochi: IEEE, 2023. P. 330–334.
This article describes a hardware and software complex for prototyping networks on a chip (NoCs) using multiple FPGAs. The rationale for using FPGAs to verify the RTL model of NoCs is given. The necessary software has been developed to automate the generation of configuration files (bitstream) for FPGA. The software divides the description of the ...
Added: June 13, 2024
Mikhail Yu. Romashikhin, , in: Proceedings 2024 International Russian Smart Industry Conference (SmartIndustryCon), 25-29 March 2024.: Sochi: IEEE, 2024. P. 104–108.
This article describes the implementation of regular topologies for networks-on-chip. The complexity of network development and its main parameters depend on the choice of topology. The rationale for the influence of topology on network bandwidth is given. Software that automates the generation of configuration files (bitstream) for the implementation of networks-on-chip with different topologies and ...
Added: May 13, 2024
Dzhanashia K., Oleg Evsutin, Multimedia Tools and Applications 2024 Vol. 83 No. 20 P. 58855–58874
Watermarking is a widespread technique for information protection and an invisible alternative to quick response codes. The literature mainly considers software implementations of watermarking methods, even though there are applications for which hardware watermarking solutions become preferable or the only possible option due to increased speed, power, or information safety requirements. A convenient, flexible, and ...
Added: December 14, 2023
Баран Е. Д., Romanov A., М.: ДМК Пресс, 2023.
В этой книге изложены основы проектирования реконфигурируемых систем в среде графического программирования LabVIEW, дополненной модулем LabVIEW FPGA. Приведен обзор разновидностей ПЛИС, модулей ввода-вывода классической архитектуры и модулей с реконфигурируемыми каналами ввода-вывода производства National Instruments. Рассмотрены основные компоненты и инструменты среды проектирования, на реальных примерах показана методика разработки и отладки распределенных и встраиваемых систем измерения, управления ...
Added: November 4, 2023
Popov M., Shishova M., Romanov A., , in: 2023 International Russian Automation Conference (RusAutoCon) 10-16 Sept. 2023.: Sochi: IEEE, 2023. P. 182–186.
The article considers the method of using multi-gigabit transceivers, which are part of the Spartan-6 FPGA, to build a data transfer channel using optical fiber as a physical medium. An example of applying the described method to create a data transmission channel with a maximum speed of up to 2.5 Gbps for operation as part of ...
Added: November 4, 2023
Popov M., Orlova K., Romanov A., , in: 2023 International Conference on Industrial Engineering, Applications and Manufacturing (ICIEAM).: Sochi: IEEE, 2023. P. 692–696.
The article presents a method of video output subsystem’s development with an ultra-high resolution (2560 x 1440 pixels and higher) support, a method for assessing the permissible video mode parameters and setting drivers, as well as an example of successful implementation of such a subsystem based on entry-level chips of the Zynq-7000 family. The features ...
Added: July 30, 2023
Измайлова Л. Г., Белоруков А. М., Romanov A., Проблемы разработки перспективных микро- и наноэлектронных систем (МЭС) 2022 № 4 С. 117–121
Remote laboratories are of growing interest to researchers around the world. Such laboratories are mainly created for specific learning conditions, so it is impossible to fully use a third-party laboratory for conducting online classes at the MIEM, HSE University, in disciplines where FPGAs (programmable integrated logic circuits) are used. The proposed solution is a remote ...
Added: December 7, 2022
Markov D., Romanov A., , in: 2022 International Ural Conference on Electrical Power Engineering (UralCon).: IEEE, 2022. P. 180–184.
RISC-V is a new and rapidly developing instruction set architecture, the main feature of which is its openness for the free use. For this reason, RISC-V is becoming more and more popular among companies with a wide range of specializations, both with hardware and software developers. The RISC-V architecture specification defines a set of standard ...
Added: November 18, 2022
Romanov A., Communications of the ACM 2022 Vol. 65 No. 10 P. 8–9
InnovateFPGA: Wrong Strategy Drives One of the Best FPGA Development Contests into Crisis
On June 23, 2022, the Grand Final of one of the key international FPGA design contests—www.innovatefpga.com
—was held in San Jose, CA. Writing on the eve of this important event, I would like to share my views on this contest:
What it was, what it has become, and why the crisis has happened. ...
Added: October 3, 2022
A. Lorens, G. Petukhov, I. Romanova, , in: 2022 International Russian Automation Conference (RusAutoCon).: IEEE, 2022. P. 623–627.
This paper presents the development of the remote stand for the HSE MIEM CAD Laboratory, which allows students to do laboratory work asynchronously. Currently, there is not enough face-to-face work of students in educational laboratories; it is important to be able to use the equipment of laboratories at any time, not limited to the time ...
Added: October 3, 2022