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News
November 10, 2026
Physicists Train AI to Optimise Particle Beams in Accelerators
Researchers from the AI and Digital Science Institute at the HSE Faculty of Computer Science and the Budker Institute of Nuclear Physics at the Siberian Branch of the Russian Academy of Sciences have developed RLABC (Reinforcement Learning for Accelerator Beamline Control), a framework that uses reinforcement learning to identify optimal settings for a particle accelerator. In a computer simulation, RLABC optimised the accelerator's parameters to achieve a particle transmission rate of 70%. The study has been published in Computer Physics Communications.
November 9, 2026
'Organ-on-a-Chip Technology Could Eliminate the Need for Animal Testing'
The Laboratory of Molecular Physiology at the HSE Faculty of Biology and Biotechnology investigates how molecular regulators known as microRNAs control gene expression and contribute to the development of diseases, including cancer, viral and inflammatory conditions, and pregnancy complications. At HSE University, researchers develop organ-on-a-chip models: miniature devices containing living cells that mimic the functions of human organs, such as the placenta and intestines. These models help researchers understand how diseases develop and how drugs affect them. HSE News Service spoke with Evgeny Knyazev, Head of the Laboratory.
November 9, 2026
Flattened Terrain Models Underestimate Vehicle-to-Vehicle Communication Outages
Researchers at HSE MIEM have shown that widely used simulators of vehicle-to-vehicle communication significantly overestimate its reliability because they assume flat terrain. When terrain features, bridges, and tunnels are taken into account, the outage rate on a mountain serpentine road rises from 21% to 30%, on an overpass from 20% to 33%, and in a tunnel from 0% to 80%. The results have been published in Future Transportation.

 

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Hardware-Software Complex for Network-on-Chip Prototyping Using Multiple FPGAs

IEEE Access. 2026. Vol. 14. P. 7921–7931.
Mikhail Y. Romashikhin, Aleksandr Y. Romanov

This paper presents a hardware-software multi-FPGA complex designed for hardware prototyping of networks-on-chip (NoCs). The rationale for the use of multiple FPGAs for NoC prototyping is given. The architecture of the complex and its components–the software part generating top-level files and configuration files describing the NoC for several FPGAs, hardware part consisting of interfacing switches between FPGAs, SoM modules with FPGAs, printed circuit board connecting the modules by a data bus–were developed. The work of the multi-FPGA complex developed was tested by calculating the examples of parallel computing tasks. The calculation of 100 digits of the π number by the Madhava series, Monte-Carlo method, and solution of the system of linear equations were chosen as a task of parallel calculations. The evaluation of benchmark developed showed that the multi-FPGA complex is suitable for NoC prototyping of parallel calculations and can be used in solving a variety of engineering problems besides NoC prototyping.

Research target: Electronics and Electrical Engineering Computer Science
Language: English
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Keywords: автоматизация проектированияпараллельные вычисленияparallel computingdesign automationFPGAПЛИСпрототипированиеСистема на кристаллесеть на кристаллеsystem-on-chipNoC benchmark network-on-chip prototyping
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