Hardware-Software Complex for Prototyping NoCs Using a Few FPGA Chips

P. 330–334.

Mikhail Romashikhin, Romanov A.

This article describes a hardware and software complex for prototyping networks on a chip (NoCs) using multiple FPGAs. The rationale for using FPGAs to verify the RTL model of NoCs is given. The necessary software has been developed to automate the generation of configuration files (bitstream) for FPGA. The software divides the description of the network-on-chip into two FPGAs, synthesizes, implements and creates configuration files. To connect two FPGAs, built-in routers have been developed (included by software in the RTL model NoC). Proposed router based on the bus and Ethernet is the core of the prototyping complex to transfer an array of signals from one FPGA to another through serialization of signals and their subsequent deserialization.

Keywords: automation, verification, FPGA, NoC, RTL

Publication based on the results of: Automation of networks-on-chip modeling (2023)

In book

2023 International Russian Automation Conference (RusAutoCon) 10-16 Sept. 2023

Sochi: IEEE, 2023.