Исследование влияние температуры на устойчивость КМОП КНИ ячеек памяти к воздействию одиночных тяжелых частиц
The multi-level methodology for CMOS SOI/SOS IC element parameterization for VLSI radiation hardness prediction by CAD systems is developed. The methodology includes semiconductor technology simulation, CMOS SOI/SOS MOSFET device simulation with radiation effects, irradiated test structures investigation, radiation dependent SPICE model parameter extraction with ICCAP. The measured data of irradiated MOSFET test structures is used for TCAD calibration and SPICE model creation. The results show a good correlation between the simulated with the developed models and measured IC and VLSI response to the total dose and other components of the radiation environment.
The models of electrophysical effects built-into Sentaurus TCAD have been tested. The models providing an adequate modeling of deep submicron high-k MOSFETs have been selected. The gate and drain leakage currents for 45 nm MOSFETs with polysilicon gate oxide and SiO2, SiO2/HfO2 and HfO2 gate dielectrics have been calculated using TCAD. It has been shown that the replacement of the traditional SiO2 gate by an equivalent HfO2 dielectric reduces the gate leakage current by several orders of magnitude due to the elimination of the impact of the tunneling effect. Besides, the threshold voltage, saturation drain current, mobility, transconductance, etc., degrade within a range of 10–20%.
For the correct accounting of joint effects of radiation and temperature on characteristics of MOSFETs with the help of TCAD system the nonlinear correction coefficient which considers change of concentration of traps from temperature is entered into model of traps volume density in oxide.
A special RAD-THERM version of TCAD subsystem based on Sentaurus Synopsys platform taking into account different types of irradiation (gamma-rays, neutrons, electrons, protons, single events) and external/internal heating effects was developed and validated to forecast the results of natural experiments, and help the designer on with reliability guarantee. The radiation- and temperature-induced faults were modeled and simulated for Si/SiGe BJTs/HBTs and bulk/SOI MOSFETs as BiCMOS LSI’s components. The causes of device parameter degradation were discussed.
The sub-100-nm CMOS process with a high-κ gate dielectric is one of the key technologies for the fabrication of digital, analog, and RF VLSI circuits and on-chip systems. The influence of ionizing radiation on 45-nm MOS transistors with a high-κ dielectric fabricated using the bulk-silicon and SOI technologies is simulated. Effects induced by the substitution of SiO2 with a high-κ dielectric are noted. The processes of selection and tuning of physical models for the simulation of high-κ MOS transistors in the Sentaurus TCAD are outlined. A set of new physical semiempirical models introducing the dependence of radiation-sensitive parameters (carrier lifetime, carrier mobility, charge density in the bulk of SiO2 and HfO2 and at the HfO2/Si interfaces) on the irradiation dose is developed. Nanoscale bulk and SOI MOS transistors with a high-κ dielectric are simulated. It is demonstrated that an increase in the drain current after irradiation in nanoscale SOI structures is induced by the charge accumulation in the side oxide. An acceptable fit between the simulation results and the experimental data is obtained. The simulation results confirm that the leakage current is suppressed (compared to common MOS transistors with SiO2) in sub-100-nm MOS transistors with a high-κ dielectric. However, the other important parameters of sub-100-nm MOS transistors with a high-κ dielectric are more sensitive to ionizing radiation.