Approach to creating a memory array constructed on two different algorithms to provide basic memory - R-trigger in transition circuitry is described. The results of a successful computer simulations for two one-layer nanostructures for memory arrays with high information density are given. The fundamental importance is the implementation of a single-layer nanostructures storage elements, which greatly simplifies and reduces the cost of the production process memory array on these nanostructures. Notes biosimilar mathematical models developed memory elements.
The paper deals with SPICE models of varying complexity for analyzing the heavy (nuclear) particles impact on CMOS circuits. For the version of the model that takes into account the influence of the electric bias on the parameters of the current pulse, expressions have been given for evaluating the main model parameters, depending on the parameters of the particle track and the structure of the MOS transistors. The influence of MOSFET scaling on SEU and SEE model parameters has been shown. Comparison of single event current pulses for the described model and data from the literature with different sizes have been presented and analyzed.
CMOS SOI cells transients were simulated using device (TCAD) and circuit (HSPICE) software tools taking into account the self-heating effects. Effect of signal cycle duration on transistors temperature was analyzed. MOSFET structures electrical and thermal parameters were defined from the TCAD simulation results and than were used for cell circuit simulation with HSPICE.