Разработка гибридной модели сети на кристалле
The article presents Java and HDL-models, which are the basis of the new hybrid NoC model. Based on it, modeling of mesh, torus topologies and two-dimensional circulant for NoC was carried out.
The article gives a brief description of NoC simulator NoCTweak, based on SystemC. Mesh NoC simulation shows that the central location of "hot spots" allows up to 9% reduction in the delay of packets, up to 15.2% – in energy consumption for each packet transmission and up to 19.5% increase of the network capacity.
The comparative analysis of different approaches to modeling of networks on chip (SoC) is provided in the article. The basic directions of exploratory research topics of SoC are defined and it is shown that modeling, analysis and simulation of SoC are basical to conduct other researches.
The typical approaches to modeling of the SoC and examples of their applications, advantages and disadvantages are characterized. They are: 1) analytical modeling (obvious approach, which does not require the use of special computer-aided design, but the analysis of such models is difficult because of their complexity and non-linearity behavior of SoC); 2) high‑level simulation (applicable to most destinations of SoC research, where there is no reference to the hardware implementation and it is necessary to get the quick simulation results with sufficient accuracy); 3) low-level HDL-modeling (it has a high accuracy, model adjustability and the possibility to synthesize the SoC, but requires a lot of time for the development of models and simulation).
The use of SystemC language for modeling SoC that enables to reduce defects and combine the advantages of low-level and high-level approaches is proposed. Modeling with SystemC is a universal approach applicable to all areas of exploratory research on the SoC.
On the basis of an integrated network-on-chip (NoC) topologies optimality criterion, as well as applying the adjacency matrix to describe NoC topologies, exhaustive search method and its modification by using branch and bound and Monte Carlo methods are extended to the synthesis of NoC quasi-optimal topologies. Designed ScaNoC suboptimal topology synthesis algorithm is implemented on a high-level programming language which makes it possible to generate quasi-optimal topological solutions in accordance with the requirements to reduce hardware costs and the average distance between nodes. Proposed quasi-optimal topologies synthesis algorithm improvement by using the method of parallel computing allows speeding up the process of synthesis to 2117 times and getting topologies with the number of nodes up to 18.
This article gives a review of existing methods of designing of networks‑on‑chip (NoC), based on the approach that makes the projection of the characteristic task graph on a given regular topology. The general problem of NoC synthesis is characterized. The network topology can be either specialized and selected depending on the tasks to be performed or can be known in advance, in most cases, a regular topology. The method of NoC synthesis by adjusting for a specific task is analyzed. The advantages and disadvantages of this approach and the effect, achieved by its use for various implementations of NoCs are shown. The way to improve the NoC synthesis by using pre-defined irregular topologies with better characteristics is proposed.
The different approaches to the optimization of network communications subsystem on a chip are considered. The mesh and pseudo-optimal topologies with 8 and 9 nodes using System Verilog library Netmaker are modelled. It is shown, that mesh topologies of rectangular form are less efficient, than square ones; pseudo-optimal topologies have a higher threshold of saturation compared to the mesh and they have no restrictions on the number of nodes. Figs: 3. Ref.: 8 titles.
The analysis of quasi-optimal and regular topologies of networks-on-chip by their synthesis and HDL-simulation is performed. The simulation results and resource costs comparison show the effectiveness of quasi-optimal topologies in the design of networks with the number of nodes and connecting lines which cannot be achieved when using typical regular topologies.