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Разработка гибридной модели сети на кристалле
Системный администратор. 2019. № 07-08. С. 110-114.
The article presents Java and HDL-models, which are the basis of the new hybrid NoC model. Based on it, modeling of mesh, torus topologies and two-dimensional circulant for NoC was carried out.
Romanov A., Tumkovskiy S., Иванова Г. А., Вестник РГРТУ 2015 Т. 2 № 52 С. 61-66
A review of the networks-on-chip modeling methods is given. A high-level model of networks-on-chip based on the programming language Java, which helps to accelerate the modeling process by several orders, compared to HDL‑models is developed. The results of simulation of networks-on-chip based on regular and quasi-optimal topologies with the number of nodes up to 100 ...
Added: June 21, 2015
Romanov A., Вестник Национального технического университета Харьковский политехнический институт. Серия: Информатика и моделирование 2012 Т. 38 № 18 С. 156-162
The different approaches to the optimization of network communications subsystem on a chip are considered. The mesh and pseudo-optimal topologies with 8 and 9 nodes using System Verilog library Netmaker are modelled. It is shown, that mesh topologies of rectangular form are less efficient, than square ones; pseudo-optimal topologies have a higher threshold of saturation ...
Added: February 15, 2015
Романов О. Ю., Лисенко О. М., Наукоємні технології 2014 Vol. 1 No. 21 P. 49-54
The comparative analysis of different approaches to modeling of networks on chip (SoC) is provided in the article. The basic directions of exploratory research topics of SoC are defined and it is shown that modeling, analysis and simulation of SoC are basical to conduct other researches.
The typical approaches to modeling of the SoC and examples ...
Added: October 31, 2014
Romanov A. Yu., Ivannikov A. D., Romanova I., , in : 2016 IEEE 36th International Scientific Conference on Electronics and Nanotechnology, ELNANO 2016 - Conference Proceedings. : Kiev : NTUU "KPI", 2016. P. 300-303.
This paper proposes an approach to the synthesis and modeling of networks-on-chip (NoCs) by using the NoCSimp library based on a simplified wormhole router with central buffer and without virtual channels. The analysis of the results of simulation and synthesis of NoCs with regular and quasi-optimal topologies with number of nodes 8 and 9 is ...
Added: April 25, 2016
Romanov A., Romanova I., Ivannikov A., , in : Proceedings of XV IEEE East-West Design & Test Symposium (EWDTS'2017). : Piscataway : IEEE, 2017. P. 1-6.
On the basis of an integrated network-on-chip (NoC) topologies optimality criterion, as well as applying the adjacency matrix to describe NoC topologies, exhaustive search method and its modification by using branch and bound and Monte Carlo methods are extended to the synthesis of NoC quasi-optimal topologies. Designed ScaNoC suboptimal topology synthesis algorithm is implemented on ...
Added: October 5, 2017
Romanov A., Вестник Национального технического университета Харьковский политехнический институт. Серия: Информатика и моделирование 2011 Т. 36 № 17 С. 149-155
The main advantages and disadvantages of classical topologies of networks on chip (NoC) are considered. The algorithm for finding optimal topologies in accordance with the restrictions on the diameter and maximum degree of optimization on the number of connections and the average distance proposed and implemented in software. The optimized topologies for the NoCs with ...
Added: February 15, 2015
Романов О. Ю., Проблеми iформатизацii та управлiння 2012 No. 3 (39) P. 124-129
The analysis of quasi-optimal and regular topologies of networks-on-chip by their synthesis and HDL-simulation is performed. The simulation results and resource costs comparison show the effectiveness of quasi-optimal topologies in the design of networks with the number of nodes and connecting lines which cannot be achieved when using typical regular topologies. ...
Added: February 18, 2015
Феськов Д. О., Романов О. Ю., Короткий Є. В., Проблеми iформатизацii та управлiння 2013 No. 2 (42) P. 118-123
The review of different approaches to the simulation of the networks-on-chip (NoC) is performed. The simulator of the NoC where the topology is set with the matrix of connections between the routers that manage the traffic by means of the routing tables is developed. The capabilities of the NoC simulator are examined and the results ...
Added: February 18, 2015
Ryazanova A.E., Amerikanov A.A., Lezhev E.V., Journal of Physics: Conference Series 2019 Vol. 1163 No. 1 P. 1-7
This work includes a review of MIPS architecture processor cores and a review of network topology consisting of routers. It was demonstrated by realization of 2 multiprocessor systems developed on the basis of mesh topology using modified schoolMIPS soft-processor cores, in which architecture additional blocks and instructions were added, and routers with XY routing. As ...
Added: June 24, 2019
Лысенко А. Н., Romanov A., Вестник Национального технического университета Харьковский политехнический институт. Серия: Информатика и моделирование 2011 Т. 17 № 16 С. 86-92
Various approaches to networks on chip organizing are considered. Тhe main drawback of networks on chip packet switching is identified – an excessively large buffers amounts of input and output buffers of routers. The new router architecture with improved resource consumption and high speed action is offered. Figs: 5. Ref.: 12 titles. ...
Added: February 15, 2015
Amerikanov A., В кн. : Проблемы разработки перспективных микро- и наноэлектронных систем – 2021 (МЭС-2021). Вып. 1.: ИППМ РАН, 2021. С. 39-45.
This work is devoted to the automation of the process of high-level modeling of network-on-chip (NoC). The main stages of designing NoC are considered. Highlighted the place of high-level modeling in the process of designing NoC. A review and classification of high-level NoC models is carried out. The main parameters of the models, based on ...
Added: August 28, 2021
Romanov O., Electronics and Communications 2014 Vol. 19 No. 5(82) P. 53-56
The synthesis of network-on-chip topologies, based on the evolutionary computations method is proposed. The optimality criteria of the network-on-chip topologies and a new class of quasi-optimal topologies are proposed. The requirements for quasi-optimal topologies are defined. The genetic algorithm GeNoC for the synthesis of quasi-optimal networks-on-chip topologies with the number of nodes up to 100 ...
Added: March 9, 2015
Romanov A., Информационные технологии 2016 Т. 22 № 7 С. 498-503
This article gives an analysis of the effect of geometric shape of the topology and «hot spots» placement on the effectiveness of networks-on-chip. For this reason, a review of the main approaches to the modeling of networks-on-chip was made and the approach for networks on-chip modeling by using SystemC NoCTweak networks-on-chip simulator. The analysis of ...
Added: October 8, 2015
Schegoleva M. A., Romanov A. Yu., Lezhnev E. V. et al., Journal of Physics: Conference Series 2019 Vol. 1163 No. 1 P. 1-7
The development of multi-core processor systems is a demanded branch of science and technology. The appearance of processors with dozens and hundreds of cores poses to the developers the question of choosing the optimal topology capable to provide efficient routing in a network with a large number of nodes. In this paper, we consider the ...
Added: May 9, 2019
Завьялов А. О., Lezhnev E., В кн. : Межвузовская научно-техническая конференция студентов, аспирантов и молодых специалистов им. Е.В. Арменского. : М. : МИЭМ НИУ ВШЭ, 2019. С. 95-96.
В работе представлена реализация генерируемой сети
на кристалле с различными параметрами на языке Verilog.
Доступные на данный момент топологии: меш, тор и
циркулянт 2 порядка. Доступными параметрами для
настройки являются: количество узлов, размер буфера
маршрутизаторов, параметры передаваемых пакетов,
частота их генерации, специфические параметры для
каждой топологии и настройки сетевого трафика. ...
Added: October 29, 2019
Романов О. Ю., Яганов П. О., , in : Информатика, математика, автоматика: 2014. Материалы научно-технической конференции. : Сумы : СумДу, 2014. P. 146-146.
By applying the methods of regression analysis of the synthesized function, which allows you to set the optimal parameters of irregular topologies of networks on chip (NoC) by the maximum and the average distance between the nodes to the number of nodes from 6 to 16. The analysis of the resulting function on the extremums ...
Added: November 1, 2014
Романов А. Ю., В кн. : Новые направления развития приборостроения: материалы 5-й Международной студенческой научно-технической конференции. : Мн. : БНТУ, 2012. С. 43-43.
Развитие микроэлектроники приводит к все большему усложнению измерительных систем. Наиболее перспективной архитектурой таких систем является построение их в виде базового вычислительного узла для обработки информации, соединенного с датчиками. Вычислительный узел состоит из системы внешних интерфейсов для приема сигналов с датчиков, вычислительного ядра для обработки информации и узлов накопления принятых данных. Центральный узел может быть подключен ...
Added: November 1, 2014
Романов А. Ю., В кн. : Информатика, математика, автоматика: 2012. Материалы научно-технической конференции. : Сумы : СумДу, 2012. С. 214-214.
Применение квазиоптимальных топологий позволяет проектировать эффективные СтнК с любым количеством узлов и заданным количеством соединений. Маршрутизация в таких сетях организуется с помощью локальных таблиц маршрутизации, размещенных в каждом роутере. Отсутствие детерминистических алгоритмов маршрутизации может привести к повышению вероятности дедлоков и ухудшения пропускной способности сети. Поэтому нами предложен алгоритм формирования таблиц маршрутизации путем поиска кратчайшего пути ...
Added: November 1, 2014
Romanov A., Вестник Южно-Уральского государственного университета. Серия: Компьютерные технологии, управление, радиоэлектроника 2015 Т. 15 № 1 С. 133-139
The article gives a review of existing methods of networks-on-chip design, based on the approach, in which the projection of the characteristic tasks graph is performed on a given regular topology. The general problem of the synthesis of networks-on-chip is characterized. The network topology can be foreknown (usually a regular topology) or selected in accordance ...
Added: February 5, 2015
Романов А.Ю., Сидоренко М.В., Монахова Э. А., Информационные технологии 2020 Т. 26 № 1 С. 22-29
The paper presents the implementation of a dynamic routing algorithm intended for use in networks-on-chip with a three-dimensional circulant topology of type C(N; s1, s2, s3). Compared with the classical algorithms A* or Dijkstra, the proposed algorithm does not require to calculate the entire path of the packet, but calculates the port number to which ...
Added: November 13, 2019
Lezhnev E., Проблемы разработки перспективных микро- и наноэлектронных систем (МЭС) 2021 № 1 С. 46-50
The process of designing a network-on-chip communication subsystem is a complex and time-consuming process, the task of which is to select the optimal characteristics in a given range of values. Although low-level modeling is time-consuming compared to high-level, but only this process allows to get the exact characteristics of the network. Comprehensive research, which is ...
Added: February 6, 2023
Yaganov P., Pavlov L., Romanov O., Science-Based Technologies. Science Journal. Ukraine 2013 Vol. 20 No. 4 P. 394-397
The main approaches to the synthesis of networks-on-chip based on regular and specialized topologies are analyzed. The optimality criteria of the topologies of networks-on-chip and a new class of quasi-optimal topologies and methods for their synthesis are proposes. The requirements for quasi-optimal topologies are defined. By using the mathematical methods of optimization the analysis of ...
Added: October 23, 2014
Романов А.Ю., В кн. : Инновации на основе информационных и коммуникационных технологий: Материалы международной научно-практической конференции, 2014. : М. : НИУ ВШЭ, 2014. С. 184-186.
The article gives a brief description of NoC simulator NoCTweak, based on SystemC. Mesh NoC simulation shows that the central location of "hot spots" allows up to 9% reduction in the delay of packets, up to 15.2% – in energy consumption for each packet transmission and up to 19.5% increase of the network capacity. ...
Added: October 16, 2014
Martynova A., Romanov O., , in : Innovations in science and technology. IX International students conference. Abstracts. Vol. 2.: Kiev : NTUU "KPI", 2012. P. 111-112.
The development of modern technologies has led to the fact that a pretty huge
number of transistors have become available on one crystal of the Electrically
Programmable Logic Device (EPLD) and allowed developers to build difficult multinuclear
systems named Multiprocessor Systems-on-Chip (MPSoC). The most progressive method
of connection of kernels together (to join them in a network) is network-on-chip ...
Added: November 1, 2014