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Свободная от дедлоков маршрутизация в сетях на кристалле с циркулянтными топологиями
С. 99–105.
In book
Вып. 3. , ИППМ РАН, 2021.
Stukach O., В кн.: Международная научно-техническая конференция РЭиС-2025Т. 1.: Омский научно-исследовательский институт приборостроения, 2025. С. 124–126.
На основе идеологии нечёткой логики предложены алгоритмы и набор правил для выявления перегрузок маршрутизаторов сети на кристалле (Network-on-Chip, NoC). Разработанные алгоритмы позволяют рассчитывать вероятность перегрузки маршрутизаторов и для различных сценариев нагрузки строить тепловые карты состояния сети. Многочисленные примеры показали эффективность предложенных алгоритмов своевременного выявления перегрузок, что даёт широкую возможность адаптации протоколов маршрутизации в сетях NoC ...
Added: March 16, 2026
Mikhail Y. Romashikhin, Aleksandr Y. Romanov, IEEE Access 2026 Vol. 14 P. 7921–7931
This paper presents a hardware-software multi-FPGA complex designed for hardware prototyping of networks-on-chip (NoCs). The rationale for the use of multiple FPGAs for NoC prototyping is given. The architecture of the complex and its components–the software part generating top-level files and configuration files describing the NoC for several FPGAs, hardware part consisting of interfacing switches ...
Added: January 22, 2026
M. Y. Romashikhin, , in: 2025 International Russian Automation Conference (RusAutoCon).: IEEE, 2025. P. 225–230.
This paper discusses the application of networks-on-chip (NoCs) for solving DSP problems. NoC is a promising architecture for organizing multicore DSP systems due to scalability and parallel data transfer between IP-cores. Filtering was chosen as a task for signal processing in this work. A technique for partitioning the filtering task into multiple network nodes. An ...
Added: October 2, 2025
Malikov M., Romanov A., IEEE Access 2025 Vol. 13 P. 148803–148815
Networks-on-chip (NoCs) widespread in computing system design are used in many applications. A critical NoC aspect is the interaction between computing cores and in particular the traffic patterns. The relevance of this work stems from the fact that traffic patterns in NoCs are poorly understood and have no general classification; and there are no universal ...
Added: September 16, 2025
Amerikanov A., Evtushenko L., Zunin V. et al., Труды Института системного программирования РАН 2025 Т. 37 № 1 С. 133–144
The paper is devoted to the description of the process of developing a new CAD architecture for high‑level modeling of NoC, as well as the remote flow of NoC design. The paper analyzes the main stages of NoC design and demonstrates the high importance of high-level modeling and its impact on the entire design process. ...
Added: November 15, 2024
M. Y. Romashikhin, I. I. Romanova, , in: 2024 International Conference on Industrial Engineering, Applications and Manufacturing (ICIEAM), 20-24 May 2024.: IEEE, 2024. P. 996–1000.
The paper provides an overview of the current state of research in the field of combinational circuits reliability and parameters. Architecture of OpenLane flow, its components and main stages of work are described. Based on this flow, the main parameters are provided that will be used for augmentation and expansion of combinational circuits dataset and ...
Added: October 12, 2024
Romanov A., Lerner A., Amerikanov A., The Journal of Supercomputing 2024 No. 80 P. 22462–22478
On-chip networks (NoCs) have become a popular choice for designing large multiprocessor architectures. Software-based emulation is often used to perform the design verifcation. However, if the considered design is sufciently large, softwarebased emulation becomes impractically slow. To avoid this limitation, multi-FPGA emulation was introduced, where multiple interconnected FPGAs collectively emulate a single circuit. The number ...
Added: June 30, 2024
Mikhail Romashikhin, Romanov A., , in: 2023 International Russian Automation Conference (RusAutoCon) 10-16 Sept. 2023.: Sochi: IEEE, 2023. P. 330–334.
This article describes a hardware and software complex for prototyping networks on a chip (NoCs) using multiple FPGAs. The rationale for using FPGAs to verify the RTL model of NoCs is given. The necessary software has been developed to automate the generation of configuration files (bitstream) for FPGA. The software divides the description of the ...
Added: June 13, 2024
Mikhail Yu. Romashikhin, , in: Proceedings 2024 International Russian Smart Industry Conference (SmartIndustryCon), 25-29 March 2024.: Sochi: IEEE, 2024. P. 104–108.
This article describes the implementation of regular topologies for networks-on-chip. The complexity of network development and its main parameters depend on the choice of topology. The rationale for the influence of topology on network bandwidth is given. Software that automates the generation of configuration files (bitstream) for the implementation of networks-on-chip with different topologies and ...
Added: May 13, 2024
Sukhov A., Romanov A., Selin M., Symmetry 2024 Vol. 16 No. 1 Article 127
In this work, the circulant topology as an alternative to 2D mesh in networks-on-chip is considered. A virtual coordinate system for numbering nodes in the circulant topology is proposed, and the principle of greedy promotion is formulated. The rules for constructing the shortest routes between the two nodes based on coordinates are formulated. A technique ...
Added: March 8, 2024
Amerikanov A., Таржанов Т. В., Romanova I. et al., Труды Института системного программирования РАН 2023 Т. 35 № 5 С. 67–80
The paper analyzes the existing methods to optimize the time costs and increase the accuracy of calculations in the high-level simulation of networks-on-chip. The description of parameters and characteristics of networks-on-chip calculated by different models is given, and their influence on the speed of high-level simulation is analyzed. Adaptation of existing methods of modeling optimization ...
Added: March 8, 2024
A. M. Sukhov, A. Y. Romanov, A. A. Amerikanov, Lobachevskii Journal of Mathematics 2023 Vol. 44 No. 12 P. 5453–5459
The paper gives a solution for the problem of the topology of the communication subsystem graph for high-performance multi-core computing systems. In this graph, each vertex is connected to four neighbors, and the number of vertices is the maximum for a given graph diameter. The solution to this problem is the family of circulants C(D(D+1)+1; ...
Added: January 6, 2024
Sukhov A., Romanov A., Глушак Е. В., Ученые записки Казанского университета. Серия: Физико-математические науки 2023 Т. 165 № 3 С. 282–293
The article discusses routing methods in two-dimensional circulant graphs (each vertex is connected to four neighboring ones). The unique group of symmetries of the circulant graph makes it possible to use it as a topology for high performance computing devices, including networks-on-chip and cluster supercomputers. It is shown that the minimum number of transitions along ...
Added: January 5, 2024
Mukosey A., Semenov A., Tretiakov A., Journal of Parallel and Distributed Computing 2024 Vol. 183 Article 104765
Several approaches and techniques exist to resolve load balancing problem in general and torus topology networks. Graph methods are natural ways to perform balancing of routing paths. A routing balancing algorithm must operate within the constraints of the underlying network architecture that limits several parameters, such as the number of logical paths in the network. In this paper, we consider a ...
Added: November 25, 2023
Romanov A., Big Data and Cognitive Computing 2023 Vol. 7 No. 2 Article 80
This article presents software for the synthesis of circulant graphs and the dataset obtained. An algorithm and new methods, which increase the speed of finding optimal circulant topologies, are proposed. The results obtained confirm an increase in performance and a decrease in memory consumption compared to the previous implementation of the circulant topologies synthesis method. ...
Added: June 4, 2023