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Quasi-3D Thermal Simulation of Multi-Chip Stack Embedding Package
Multi-chip embedded PCBs were in resent years the mainstream technology of electronic packaging size reduction and at the same time providing improved performance. Ultra-small package size obviously strongly impacts the SiP module thermal behaviour. Unfortunately the complete thermal design methodology was not developed for this technology till now. In this work the problem of thermal design is completely solved using quasi-3D approach taking into account the main features of embedded PCB constructions: 1) 3D integration of ICs and board; 2) a large number of thinned layers of different materials; 3) vertical z-axis interconnections through the package layers. A ten times decrease of central processing unit (CPU) time is achieved as compared with the full 3D solutions obtained by commercial universal 3D simulators, while saving the sufficient accuracy. The simulation error of maximal temperature T MAX determination for different types of packages is not more than 10-20%.