High temperature submicron SOI CMOS technology characterization for analog and digital applications up to 300°C

K. O. Petrosyants; Lebedev S.; L. M. Sambursky; Stakhin V.; I. A. Kharitonov; M. R. Ismail-zade; Ignatov P.

doi:10.1109/SEMI-THERM.2017.7896935

Publications

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High temperature submicron SOI CMOS technology characterization for analog and digital applications up to 300°C

P. 229–234.

Petrosyants K. O., Lebedev S., Sambursky L. M., Stakhin V., Kharitonov I. A., Ismail-zade M. R., Ignatov P.

Currently, an increasing number of applications are demanding for electronic units capable of operating reliably in the high temperature range: automotive, airplane and space vehicles, geothermal and nuclear energy generation, deep hole drilling [1]–[5]. Today there are two main trends in high-temperature electronics: 1) device sizes scaling for high performance and low-power digital applications (microprocessors, memories, logic circuits etc.), 2) increasing diversification and specialization of analog applications: high resolution ADCs, voltage references, on-engine sensors (temperature probe, thermocouple, strain gauges, frequency), single ASICs etc.

Keywords: high-temperature electronics silicon-on-insulator (SOI)temperature-dependent parameters compact modeling

In book

33rd Thermal Measurement, Modeling & Management Symposium (SEMI-THERM). PROCEEDINGS 2017

Denver: IEEE, 2017.

SPICE Modeling of GaN HEMTs in the Wide Temperature Range (−269°C…+500°C)

Petrosyants K. O., Ismail-zade M. R., Sambursky L. M., , in: 2025 31st International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), 24-26 Sept. 2025.: IEEE, 2025. P. 1–4.

The temperature range of the core industry standard ASM model for GaN HEMTs is extended from the standard commercial level (−60∘C to+150∘C) to extreme low and high level (−269∘C…+500∘C) for low- and high-temperature ICs design. This is done by including additional equations for temperature-dependent parameters. The good agreement between simulated and measured device characteristics is achieved. The RMS error is not more ...

Added: November 5, 2025

Superconducting Electronic–Photonic Platform for HEB-Based Terahertz Spectrometers

Shurakov A., Belikov I., Prikhodko A. et al., Applied Sciences (Switzerland) 2023 Vol. 13 No. 10 Article 5892

Terahertz photonic integrated circuits are becoming popular in ultrafast on-chip signal generation and processing. They outperform assemblies of electronic devices making use of metallic waveguides in term of both fabrication complexity and system losses. In this study, we report on a nearly all-dielectric hot electron bolometer mixer compatible with the technology of integrated Si photonic ...

Added: May 11, 2023

Compact SPICE Models of Sub-100 nm FDSOI and FinFET Devices in the Wide Temperature Range (-269°C … + 300°C)

Konstantin O. Petrosyants, Mamed R. Ismail-zade, Sambursky L. M., , in: 2022 28th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC).: IEEE, 2022. P. 1–4.

The temperature range of SPICE models of sub-100 nm FDSOI MOSFETs and FinFETs is extended from the standard commercial level (-60°C to +150 °C) to extreme low and high level (-200 °C … +300 °C) for low/high temperature ICs design. This is done by including additional equations for temperature-dependent parameters, and by connecting additional elements ...

Added: December 15, 2022

Dependence of Temperature and Back-Gate Bias on Single-Event Upset Induced by Heavy Ion in 0.2-μm DSOI CMOS Technology

Wang Y., Liu F., Li B. et al., IEEE Transactions on Nuclear Science 2021 Vol. 68 No. 8 P. 1660–1667

The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2- μm double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM). The physical mechanism of single-event effect ...

Added: September 26, 2021

Early Study of Transistor and Circuit Parameter Variation for 180 nm High-Temperature SOI CMOS Production Technology

Lev M. Sambursky, Mamed R. Ismail-zade, Nina V. Blokhina, , in: 2020 Moscow Workshop on Electronic and Networking Technologies (MWENT).: IEEE, 2020. P. 1–7.

In this paper, we do an early study of circuit parameter variation for temperature-resistant SOI CMOS production technology on the examples of several standard circuit fragments. Circuits electrical characteristics are simulated at several values of temperature (in the range +27…+300 °C) and with account for MOSFET parameter mismatch figures derived from measurement data. The method ...

Added: May 7, 2020

Prediction of High-Temperature Operation (up to +300°C) of Reference Voltage Source Built with Temperature-Tolerant Production Technology

Lev M. Sambursky, Dmitry A. Parfenov, Mamed R. Ismail-zade et al., , in: Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2018).: IEEE Computer Society, 2018. P. 609–613.

In this work, virtual testing of submicron SOI CMOS reference voltage source integrated circuit was conducted with regard to elevated temperature in the range up to +300°C. Based on simulation results its temperature tolerance figures were estimated. ...

Added: October 30, 2018

Automation of Parameter Extraction Procedure for Si JFET SPICE Model in the −200…+110°C Temperature Range

Petrosyants K. O., Ismail-zade M. R., Sambursky L. M. et al., , in: 2018 Moscow Workshop on Electronic and Networking Technologies (MWENT). Proceedings.: M.: IEEE, 2018. P. 1–5.

Through the analysis of JFET models with account for temperature effects, the most suitable one was selected as a basis for expanding SPICE modeling possibilities to cryogenic-to-high temperature range. Parameter extraction procedure was automated and improved using IC-CAP scripting capabilities. ...

Added: September 8, 2018

Electrical characterization and reliability of submicron SOI CMOS technology in the extended temperature range (to 300 °C)

Petrosyants K. O., Kharitonov I. A., Lebedev S. et al., Microelectronics and Reliability 2017 Vol. 79 P. 416–425

I-V characteristics and reliability parameters for the set of hardened SOIMOSFET'swith special layouts and tungsten metallization to provide additional thermal tolerance for high-temperature SOI CMOS IC's are investigated in the temperature range up to 300 °C. The reliability aspects under test for MOSFET's are threshold voltage shift, subthreshold slope and mobility degradation, gate leakage current ...

Added: February 28, 2018

Hardware-Software System for Automation of Characteristics Measurement of SOI CMOS VLSI Elements under Extreme High Temperature Conditions (up to 300°C)

Mamed R. Ismail-zade, Aleksandr Y. Romanov, Egor Y. Kuzin et al., , in: Proceedings of the 2017 IEEE Russia Section Young Researchers in Electrical and Electronic Engineering Conference (2017 ElConRus)* 2.: M.: IEEE, 2017. P. 423–428.

Hardware-software system designed for automated SOI MOSFETs characteristics measurement, processing and SPICE model parameter extraction taking into account high temperature (HT) effects (to 300°C) is presented. The essence of the system is comprised of a set of selected measurement instru-ments, measurement and data processing methods with the pur-pose of SPICE model library creation in lightly ...

Added: March 6, 2017

Temperature Characterization of Small-Scale SOI MOSFETs in the Extended Range (to 300°C)

Konstantin O. Petrosyants, Sergey V. Lebedev, Sambursky L. M. et al., , in: Proceedings of the 22nd International Workshop on Thermal Investigations of ICs and Systems (Therminic 2016).: IEEE, 2016. P. 250–254.

In this work, results of electrical measurements and their analysis are demonstrated for a small-scale 180-nm SOI CMOS technology in the extended temperature range (up to 300°C). Comparison with high temperature electrical characteristics of 0.5 um technology is drawn. Modified model for SOI MOSFETs, based on BSIMSOI model is developed and model parameters are extracted for SPICE simulation ...

Added: November 1, 2016