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Regular version of the site

Book chapter

TCAD-SPICE simulation of MOSFET switch delay time for different CMOS technologies

P. 188-190.
Petrosyants K., Orekhov E. V., Popov D., Kharitonov I. A., Sambursky L. M., Yatmanov A., Voevodin A., Mansurov A.

A comparison of delay time for n- and p- MOSFETs switches with silicon on sapphire (SOS), silicon on insulator (SOI) and bulk silicon structures is presented. Two step TCAD-SPICE simulation procedure was used to define delay time for the set of 3.0…0.25 um MOSFETs fabricated by three mentioned technologies. It was shown that 0.5 um Peregrine UTSi SOS n- and p-MOSFET provided the td reduction of 220-240% in comparison with bulk silicon and 20-25%with SOI.

In book

TCAD-SPICE simulation of MOSFET switch delay time for different CMOS technologies
Edited by: В. Хаханов. Kharkov: Kharkov national university of radioelectronics, 2011.