Proceedings of IEEE East-West Design & Test Symposium (EWDTS’11)
The main target of the IEEE East-West Design & Test Symposium (EWDTS-2011) is to exchange experiences between scientists and technologies of Eastern and Western Europe, as well as North America and other parts of the world, in the field of design, design automation and test of electronic circuits and systems. EWDTS’11 covers the following topics:
- Analog, Mixed-Signal and RF Test
- Analysis and Optimization
- EDA Tools for Design and Test
- Failure Analysis, Defect and Fault
- Modeling & Fault Simulation
- Power Issues in Testing
- Reliability of Digital Systems
- Thermal, Timing and Electrostatic Analysis of SoCs and Systems on Board
The effects of neutron irradiation on both Si bipolar junction transistor (BJT) and SiGe heterojunction transistor (HBT) are investigated using Synopsys TCAD tool. The carrier lifetime degradation under irradiation models are included in the program. For SiGe HBT at fluences as high as 10**15 cm-2 the degradation of peak current gain is less than 40%, and the device maintains a peak current gain of 80 100 after 10**15 cm-2. The simulation results are in good agreement with experimental data.
New quasi – 3D numerical model for thermal analysis of the BGA packages is presented. The general 3D heat transfer problem is correctly transformed to the set of 2D equations for temperature distributions in different layers of the package. The complexity and CPU time of the thermal analysis are many times reduced. The results of BGA package thermal modeling are presented.
The corrections of the methodology of power BJT and MOSFET transistor models parameter extraction taking into account the self heating effects are presented. For BJT these corrections are included into VBIC model parameter extraction process. For MOSFET current generator connected to standard SPICE MOS model is proposed to take into account drain current growth with transistor temperature.
The effects of neutron irradiation on both Si bipolar junction transistor (BJT) and SiGe heterojunction transistor (HBT) are investigated using Synopsys/ISE TCAD tool. For this purpose the carrier lifetime degradation under irradiation models are included in the program. It was established that at fluence 4×1013 cm-2 the Si BJT exhibited a degradation in current gain of 50% for high level and 80% for low level of E-B junction injection. For SiGe HBT at fluences as high as 1015 cm-2 the degradation of peak current gain is less than 40%, and the device maintains a peak current gain of 80 – 100 after 1015 cm-2. The cut-off and maximum oscillations frequencies are small sensitive to neutron irradiation. The simulation results are in good agreement with experimental data.
A comparison of delay time for n- and p- MOSFETs switches with silicon on sapphire (SOS), silicon on insulator (SOI) and bulk silicon structures is presented. Two step TCAD-SPICE simulation procedure was used to define delay time for the set of 3.0…0.25 um MOSFETs fabricated by three mentioned technologies. It was shown that 0.5 um Peregrine UTSi SOS n- and p-MOSFET provided the td reduction of 220-240% in comparison with bulk silicon and 20-25%with SOI.