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August 12, 2026
‘I Would Like My Research to Help Make the World a Calmer and Better Place
Whatever task Saraa Ali, Junior Research Fellow at the Laboratory of Methods for Big Data Analysis (LAMBDA) of the AI and Digital Science Institute (HSE Faculty of Computer Science), is working on, she thinks about how it can benefit people. She told the Young Scientists of HSE University project about her large family, diagnosing three-phase motors, and her dream of building a children’s home in her native country.
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Compact SPICE Models of the Standard Layout Fragments in LSI Interconnections

P. 580–584.
Petrosyants K.O., Ryabov N.I., Batarueva E.I.

Authors propose a compact SPICE model of LSI interconnections providing high accuracy of simulation in a time domain with considerable reduction of simulation time. Both straight sections of interconnections, bends with angles 90° and 135° and also T-shaped branches of interconnections are considered. The interconnection model in the form of a multilink RC circuit is taken as a basis. For use in a time domain, the two-section model, both long straight sections of interconnections, and bends is offered. The multi-section RC circuits and the equivalent two- section model were simulated. Using the two-section model, CPU time is reduced by 20%. At the same time the error of the two-section model is 2% in a time domain.

Language: English
Full text
DOI
Keywords: simulationSPICE modelstime delayLSI interconnections

In book

Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2018)
IEEE Computer Society, 2018.
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