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## Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2018)

An extended version of MOSFET RAD SPICE model providing combined account for aging and total dose effects is described. The model uses summation of radiation induced (depending on dose rate, irradiation time, electrical bias) oxide and interface traps densities and interface densities produced by hot electrons to calculate MOSFET characteristics. The model was built using macromodeling approach, standard SPICE models for MOSFETs (BSIMSOI or EKV) and model parameters dependences on electrical stress and total dose irradiation factors. The developed model accounts for enhanced degradation due to combined TID and electrical stress conditions.

In this work, virtual testing of submicron SOI CMOS reference voltage source integrated circuit was conducted with regard to elevated temperature in the range up to +300°C. Based on simulation results its temperature tolerance figures were estimated.

An approach to analyze PLL jitter under noise excitations of the different origin is considered in the paper. Both internal device noise and external switching noise can be captured by the proposed approach. Jitter evaluation is provided by obtaining phase transfer functions (TF) from any circuit node to the PLL output. Unlike previous works explaining noise folding in PLL by sampling processes, this paper shows that spectrum aliasing in PLL blocks appears in both digital and analog PLL due to principal properties of Linear Periodically Time- Varying (LPTV) systems. Expressions for the evaluation TF of PLL blocks are presented. The PLL macromodel developed in the form of block diagram allowed the authors to derive the set of PLL TFs. Different approaches to the evaluation of the phase TF by additive TFs of electrical harmonics are discussed.

This paper presents a new integration technique for time-domain simulation of nonlinear electronic circuits. The new technique exploits A-stable single-step integration methods of order 1 up to 4 obtained by applying the Obreshkov formula to charge oriented circuit equations. The predictor-corrector algorithm exploited in the transient analysis for solving the initial value problem is described. The numerical examples of time-domain simulation are given which demonstrate the numerical accuracy and efficiency of the proposed technique.

Authors propose a compact SPICE model of LSI interconnections providing high accuracy of simulation in a time domain with considerable reduction of simulation time. Both straight sections of interconnections, bends with angles 90° and 135° and also T-shaped branches of interconnections are considered. The interconnection model in the form of a multilink RC circuit is taken as a basis. For use in a time domain, the two-section model, both long straight sections of interconnections, and bends is offered. The multi-section RC circuits and the equivalent two- section model were simulated. Using the two-section model, CPU time is reduced by 20%. At the same time the error of the two-section model is 2% in a time domain.

Digital LSI circuits, and digital blocks in many cases fulfill a succession of operation from limited collection. In this paper computer modeling of LSI logical circuits represents logical signals on the pins. For a computer-aided design it is very important to develop the collection of tests for digital LSI circuits for proving the successfulness of design. The most productive and economical test set could be generated if a formal description of digital block or system possible input data domain is known. The input data domain structure are analyzed and described for digital blocks and systems with finite alphabet of functions. The formal description of input data domain for each function of digital block or system are proposed. Proposed description has the form of labeled directed graph describing the sequence of input logical signals with timing constrains.

Most modern software is written in high level languages. The task of translating source code, written in high-level languages, into a representation, which can be executed on a computer system, solves by specialized programs called compilers. Errors in compilers lead to differences between the behavior of modules, resulting from the work of compilers, and behavior, defining the semantics of the original program. Such errors are very difficult to detect and correct, and their presence casts doubt on the quality of the programs generated by a compiler. Obviously, the correctness of the compiler is a strong prerequisite for reliable software created with its help [20]. This paper describes the concept of a system designed to automate the process of testing the major components of any compiler: syntax analyzer and context conditions analyzer (semantic analyzer).

The main target of the IEEE East-West Design & Test Symposium (EWDTS-2013) is to exchange experiences between scientists and technologies of Eastern and Western Europe, as well as North America and other parts of the world, in the field of design, design automation and test of electronic circuits and systems. EWDTS’13 covers the following topics:

• Analog, Mixed-Signal and RF Test

• Analysis and Optimization

• EDA Tools for Design and Test

• Failure Analysis, Defect and Fault

• Modeling & Fault Simulation

• Power Issues in Testing

• Reliability of Digital Systems

• Thermal, Timing and Electrostatic Analysis of SoCs and Systems on Board

*There have been many reports on advances in the development of learner corpora that have made it possible to effectively use these collections of texts for the benefit of the learning process. This paper lists all possible applications in English courses taught to Bachelor students of a middle-size learner corpus REALEC, which comprises student written works supplied with expert annotation of mistakes, browsing and search options, and some optional automated tagging system. Annotation in the corpus is given by either experts (mostly, EFL instructors), or by learners themselves under the supervision of their EFL instructors. As the first point, the paper argues that when EFL methodology requires that students apply the error classification in the process of annotating their peers’ essays and gradually their own essays as well, their understanding of subtle areas of grammar, vocabulary and discourse improves, and correspondingly, the number of errors in their written works decreases. The second argument concerns the tool for the development of placement and progress tests, which makes use of sentences with mistakes made by other learners – contributors to the corpus. In the suggested design of the tests sentences are automatically extracted from the same corpus, manually divided into three echelons according to the complexity of the change required in the correction of the mistake, and then administered to learners as a way of automated measurement of their proficiency in English. The submitted test is scored automatically within minutes. The third possibility considered in the research is the possibility to supplement the corpus with the platform of trainers automatically or semi-automatically set up on the basis of frequently marked errors made by a particular group of students. In conclusion we point out the ease and usefulness of the proposed applications both for EFL instructors and English learners.*

This paper considers the development of digital circuit tests using continuous models of discrete devices. An algorithm is presented which makes it possible to solve the problem of finding test sets using continuous optimization. A generalized fault model is proposed which implements a unified approach to the representation of different types of faults in test generation. The proposed approach is implemented as a software environment for research and development of fault models and algorithms for finding digital circuit tests. For testing, a system of automated test generation for constant faults of combinational circuits has been built. The performance estimation results for the software package developed for the ISCAS '85 benchmark circuits demonstrate the effectiveness of the algorithms and methods used.

Let G be a semisimple algebraic group whose decomposition into the product of simple components does not contain simple groups of type A, and P⊆G be a parabolic subgroup. Extending the results of Popov [7], we enumerate all triples (G, P, n) such that (a) there exists an open G-orbit on the multiple flag variety G/P × G/P × . . . × G/P (n factors), (b) the number of G-orbits on the multiple flag variety is finite.

I give the explicit formula for the (set-theoretical) system of Resultants of m+1 homogeneous polynomials in n+1 variables