Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2018)
An extended version of MOSFET RAD SPICE model providing combined account for aging and total dose effects is described. The model uses summation of radiation induced (depending on dose rate, irradiation time, electrical bias) oxide and interface traps densities and interface densities produced by hot electrons to calculate MOSFET characteristics. The model was built using macromodeling approach, standard SPICE models for MOSFETs (BSIMSOI or EKV) and model parameters dependences on electrical stress and total dose irradiation factors. The developed model accounts for enhanced degradation due to combined TID and electrical stress conditions.
In this work, virtual testing of submicron SOI CMOS reference voltage source integrated circuit was conducted with regard to elevated temperature in the range up to +300°C. Based on simulation results its temperature tolerance figures were estimated.
An approach to analyze PLL jitter under noise excitations of the different origin is considered in the paper. Both internal device noise and external switching noise can be captured by the proposed approach. Jitter evaluation is provided by obtaining phase transfer functions (TF) from any circuit node to the PLL output. Unlike previous works explaining noise folding in PLL by sampling processes, this paper shows that spectrum aliasing in PLL blocks appears in both digital and analog PLL due to principal properties of Linear Periodically Time- Varying (LPTV) systems. Expressions for the evaluation TF of PLL blocks are presented. The PLL macromodel developed in the form of block diagram allowed the authors to derive the set of PLL TFs. Different approaches to the evaluation of the phase TF by additive TFs of electrical harmonics are discussed.
This paper presents a new integration technique for time-domain simulation of nonlinear electronic circuits. The new technique exploits A-stable single-step integration methods of order 1 up to 4 obtained by applying the Obreshkov formula to charge oriented circuit equations. The predictor-corrector algorithm exploited in the transient analysis for solving the initial value problem is described. The numerical examples of time-domain simulation are given which demonstrate the numerical accuracy and efficiency of the proposed technique.
Authors propose a compact SPICE model of LSI interconnections providing high accuracy of simulation in a time domain with considerable reduction of simulation time. Both straight sections of interconnections, bends with angles 90° and 135° and also T-shaped branches of interconnections are considered. The interconnection model in the form of a multilink RC circuit is taken as a basis. For use in a time domain, the two-section model, both long straight sections of interconnections, and bends is offered. The multi-section RC circuits and the equivalent two- section model were simulated. Using the two-section model, CPU time is reduced by 20%. At the same time the error of the two-section model is 2% in a time domain.
Digital LSI circuits, and digital blocks in many cases fulfill a succession of operation from limited collection. In this paper computer modeling of LSI logical circuits represents logical signals on the pins. For a computer-aided design it is very important to develop the collection of tests for digital LSI circuits for proving the successfulness of design. The most productive and economical test set could be generated if a formal description of digital block or system possible input data domain is known. The input data domain structure are analyzed and described for digital blocks and systems with finite alphabet of functions. The formal description of input data domain for each function of digital block or system are proposed. Proposed description has the form of labeled directed graph describing the sequence of input logical signals with timing constrains.