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Automation of NoC throughput search in high-level modeling
P. 1–5.
This work is devoted to the development of a single environment for high-level Network-on-Chip (NoC) modeling. The developed environment includes several highlevel models and optimization methods. This concept allows for more accurate modeling and reduces simulation time. The concept of the software environment is proposed, and the requirements for added models are described. Methods for optimizing the process of high-level NoC modeling (the comparative method, parallel launch of several models, binary search method, golden section method, similarity method) are developed and tested. Modelling results are studied using the methods proposed.
Publication based on the results of:
In book
M.: IEEE, 2022.
Омаров М. Т., Маликов М. А., Amerikanov A., , in: 2026 International Conference on Industrial Engineering, Applications and Manufacturing (ICIEAM).: IEEE, 2026. P. 791–796.
High-level simulation is a critical stage for optimizing Network-on-Chip (NoC) design, enabling a reduction in time and resources at subsequent development stages. Existing tools often possess limited configuration flexibility and support a narrow set of traffic models, which complicates the evaluation of networks specialized for specific applications. This paper investigates an approach to extending NoC ...
Added: August 22, 2026
M. Y. Romashikhin, , in: 2025 International Russian Automation Conference (RusAutoCon).: IEEE, 2025. P. 225–230.
This paper discusses the application of networks-on-chip (NoCs) for solving DSP problems. NoC is a promising architecture for organizing multicore DSP systems due to scalability and parallel data transfer between IP-cores. Filtering was chosen as a task for signal processing in this work. A technique for partitioning the filtering task into multiple network nodes. An ...
Added: October 2, 2025
Amerikanov A., Evtushenko L., Zunin V. et al., Труды Института системного программирования РАН 2025 Т. 37 № 1 С. 133–144
The paper is devoted to the description of the process of developing a new CAD architecture for high‑level modeling of NoC, as well as the remote flow of NoC design. The paper analyzes the main stages of NoC design and demonstrates the high importance of high-level modeling and its impact on the entire design process. ...
Added: November 15, 2024
M. Y. Romashikhin, I. I. Romanova, , in: 2024 International Conference on Industrial Engineering, Applications and Manufacturing (ICIEAM), 20-24 May 2024.: IEEE, 2024. P. 996–1000.
The paper provides an overview of the current state of research in the field of combinational circuits reliability and parameters. Architecture of OpenLane flow, its components and main stages of work are described. Based on this flow, the main parameters are provided that will be used for augmentation and expansion of combinational circuits dataset and ...
Added: October 12, 2024
Mikhail Romashikhin, Romanov A., , in: 2023 International Russian Automation Conference (RusAutoCon) 10-16 Sept. 2023.: Sochi: IEEE, 2023. P. 330–334.
This article describes a hardware and software complex for prototyping networks on a chip (NoCs) using multiple FPGAs. The rationale for using FPGAs to verify the RTL model of NoCs is given. The necessary software has been developed to automate the generation of configuration files (bitstream) for FPGA. The software divides the description of the ...
Added: June 13, 2024
Amerikanov A., Таржанов Т. В., Romanova I. et al., Труды Института системного программирования РАН 2023 Т. 35 № 5 С. 67–80
The paper analyzes the existing methods to optimize the time costs and increase the accuracy of calculations in the high-level simulation of networks-on-chip. The description of parameters and characteristics of networks-on-chip calculated by different models is given, and their influence on the speed of high-level simulation is analyzed. Adaptation of existing methods of modeling optimization ...
Added: March 8, 2024
Rzaev E., Ryzhov A., Romanov A., , in: 2022 International Conference on Industrial Engineering, Applications and Manufacturing (ICIEAM).: Sochi: IEEE, 2022. P. 819–824.
This work is a logical continuation of previous
works related to the study of promising topologies for
networks-on-chip based on the direct and root product of
circulant graphs. In this article, we describe and compare the
static characteristics of the hierarchical method of constructing
more complex structures compared to the root and direct
products of graphs. Also in this paper, the ...
Added: June 16, 2022
Мячин Н. М., Romanov A., Монахова Э. А., В кн.: Проблемы разработки перспективных микро- и наноэлектронных систем – 2021 (МЭС-2021)Вып. 3.: ИППМ РАН, 2021. С. 99–105.
Added: November 12, 2021
Amerikanov A., Ponomarev A., , in: 2021 International Russian Automation Conference (RusAutoCon).: IEEE, 2021. P. 677–682.
Added: October 6, 2021
Lezhnev E., , in: 2021 International Russian Automation Conference (RusAutoCon).: IEEE, 2021. P. 780–784.
Added: October 6, 2021
Romanov A., Lezhnev E., Amerikanov A., , in: Proceedings of the 6th International Conference Actual Problems of System and Software Engineering (APSSE) Moscow, Russia, 12-14 November, 2019.Vol. 2514.: CEUR-WS, 2019. Ch. 107 P. 182–192.
In this paper, a review of various high-level models of networks-on-chip, their performance capabilities, and characteristics was carried out. As a result, the BookSim simulator was chosen. Application of circulant topologies for implementation of communication subsystems in networks-on-chip (NoCs) as alternatives to other regular topology was proved. The process of modifying the BookSim simulator described ...
Added: November 21, 2019