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September 11, 2026
How to Assess Students Knowledge in the Age of AI
A researcher at HSE University has proposed a flowchart to help lecturers decide how to assess students who use artificial intelligence. It shows where the use of AI should be restricted and where it can be incorporated into the learning process. The article has been published in IT Professional.
September 9, 2026
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September 9, 2026
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Universal On-Chip Network Simulator for Networks-on-Chip Development

P. 677–682.
Amerikanov A., Ponomarev A.
Language: English
Full text
DOI
Text on another site
Keywords: regular topologycirculant topologyhigh-level modelingNoCgpNOCSimUOCNS
Publication based on the results of:
Development of routing algorithms in Networks on Chip (2021)

In book

2021 International Russian Automation Conference (RusAutoCon)
IEEE, 2021.
Similar publications
User Traffic Generation for Networks-on-Chip High-Level Modeling in BookSim-based Toolset
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High-level simulation is a critical stage for optimizing Network-on-Chip (NoC) design, enabling a reduction in time and resources at subsequent development stages. Existing tools often possess limited configuration flexibility and support a narrow set of traffic models, which complicates the evaluation of networks specialized for specific applications. This paper investigates an approach to extending NoC ...
Added: August 22, 2026
Digital Filtering Algorithms for Signal Processing in NoCs
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This paper discusses the application of networks-on-chip (NoCs) for solving DSP problems. NoC is a promising architecture for organizing multicore DSP systems due to scalability and parallel data transfer between IP-cores. Filtering was chosen as a task for signal processing in this work. A technique for partitioning the filtering task into multiple network nodes. An ...
Added: October 2, 2025
САПР для удаленного высокоуровневого моделирования СтнК
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The paper is devoted to the description of the process of developing a new CAD architecture for high‑level modeling of NoC, as well as the remote flow of NoC design. The paper analyzes the main stages of NoC design and demonstrates the high importance of high-level modeling and its impact on the entire design process. ...
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This article describes a hardware and software complex for prototyping networks on a chip (NoCs) using multiple FPGAs. The rationale for using FPGAs to verify the RTL model of NoCs is given. The necessary software has been developed to automate the generation of configuration files (bitstream) for FPGA. The software divides the description of the ...
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Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip
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In this work, the circulant topology as an alternative to 2D mesh in networks-on-chip is considered. A virtual coordinate system for numbering nodes in the circulant topology is proposed, and the principle of greedy promotion is formulated. The rules for constructing the shortest routes between the two nodes based on coordinates are formulated. A technique ...
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The paper gives a solution for the problem of the topology of the communication subsystem graph for high-performance multi-core computing systems. In this graph, each vertex is connected to four neighbors, and the number of vertices is the maximum for a given graph diameter. The solution to this problem is the family of circulants C(D(D+1)+1; ...
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This article considers the usage of circulant topologies as a promising deadlock-free topology for networks-on-chip (NoCs). A new high-level model, Newxim, for the exploration of NoCs with any topology is presented. Two methods for solving the problem of cyclic dependencies in circulant topologies, which limit their applications for NoCs due to the increased possibility of ...
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The solution of the problem of organizing optimal communications in circulant networks of degree four is considered. For a family of optimal circulant networks with the minimum diameter and average distance for any number of nodes in a graph, we propose an optimal pair routing algorithm of constant complexity based on using the relative addressing ...
Added: November 18, 2022
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This work is devoted to the development of a single environment for high-level Network-on-Chip (NoC) modeling. The developed environment includes several highlevel models and optimization methods. This concept allows for more accurate modeling and reduces simulation time. The concept of the software environment is proposed, and the requirements for added models are described. Methods for ...
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This work is a logical continuation of previous works related to the study of promising topologies for networks-on-chip based on the direct and root product of circulant graphs. In this article, we describe and compare the static characteristics of the hierarchical method of constructing more complex structures compared to the root and direct products of graphs. Also in this paper, the ...
Added: June 16, 2022
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Development of routing algorithms in networks-on-chip based on two-dimensional optimal circulant topologies
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This work is devoted to the study of application of new topologies in the design of networks‑on‑chip (NoCs). It is proposed to use two‑dimensional optimal circulant topologies for NoC design, and it is developed an optimized routing algorithm with the decreased memory usage. The proposed routing algorithm was compared with Table routing, Clockwise routing, and ...
Added: January 19, 2020
Modification of the BookSim simulator for modeling networks-on-chip based on two dimensional circulant topologies
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In this paper, a review of various high-level models of networks-on-chip, their performance capabilities, and characteristics was carried out. As a result, the BookSim simulator was chosen. Application of circulant topologies for implementation of communication subsystems in networks-on-chip (NoCs) as alternatives to other regular topology was proved. The process of modifying the BookSim simulator described ...
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