Cycle-accurate multi-FPGA platform for accelerated emulation of large on-chip networks

The Journal of Supercomputing. 2024. No. 80. P. 22462–22478.

Romanov A., Lerner A., Amerikanov A.

On-chip networks (NoCs) have become a popular choice for designing large multiprocessor architectures. Software-based emulation is often used to perform the design verifcation. However, if the considered design is sufciently large, softwarebased emulation becomes impractically slow. To avoid this limitation, multi-FPGA emulation was introduced, where multiple interconnected FPGAs collectively emulate a single circuit. The number of external FPGA pins is often insufcient for emulating large network-on-chip designs accurately. As a result, the overall emulation frequency has to be severely limited. We propose a method for accelerating multiFPGA emulation by reducing the amount of data FPGAs need to transmit to each other. To achieve cycle-accurate emulation in the absence of constant transmission latency, synchronous messaging is implemented. The proposed method was tested on a functioning prototype. It is shown that the use of our method for multi-FPGA emulation of large NoC designs can reach several orders.

Keywords: communication, network-on-chip, on-chip network, multi-FPGA, inter-FPGA, hardware emulation

Publication based on the results of: Research of new classes of circulant graphs and their characteristics for designing networks-on-chip (2024)