Программируемые логические интегральные схемы (ПЛИС) для систем управления поездами
The article presents the concept of networks on chip (NoC) as a promising alternative to the communication subsystem for multiprocessor systems with bus architecture. Various approaches to modeling NoC are given and as the necessary software tools to evaluate NoC performance parameters the structure and simulation software solution for WFC-networks with virtual channels, XY-routing and various topologies are proposed. The testing of the simulator is performed by the example of the simulation of dependence of the average number of hops, needed for packets passing the network, from the dimension of NoC for mesh and torus topologies.
Are the main features of CAD software used in the development of equipment using FPGA. Is an example of job creation projects FPGA. Discusses some common problems and suggest ways to address them.
Actual trends of networks-on-chip research and known approaches to their modeling are considered. The characteristics of analytic and high- / low- level simulation are given. The programming language SystemC as an alternative solution to create models of networks-on-chip is proposed, and SystemC models speed increase methodic is observed.
Provides an overview of the different ways to implement the high-speed I/O data to the PC using FPGA based on the use of commercially available modules. The possibility of developing a specialized unit that provides the present-simplification of the equipment.
This article gives a review of existing methods of designing of networks‑on‑chip (NoC), based on the approach that makes the projection of the characteristic task graph on a given regular topology. The general problem of NoC synthesis is characterized. The network topology can be either specialized and selected depending on the tasks to be performed or can be known in advance, in most cases, a regular topology. The method of NoC synthesis by adjusting for a specific task is analyzed. The advantages and disadvantages of this approach and the effect, achieved by its use for various implementations of NoCs are shown. The way to improve the NoC synthesis by using pre-defined irregular topologies with better characteristics is proposed.
The paper describes basic methods of data compression without loss and analyzes their advantages and disadvantages. There is a hardware implementation on FPGA of compression algorithm for stream processing of information. This algorithm can be used in applications related to telecommunications networks of distributed control systems.