The automatic electro-thermal simulation has been implemented in Mentor Graphics PCB Design Flow. New program-dispatcher TransPower has been developed to control the electro-thermal calculation process, combining the programs of the electric (Analog Designer) and thermal (BETAsoft) simulation into a single cycle. As a result, the labor consumption and the PCB electro-thermal simulation time have been significantly reduced, the accuracy and reliability of calculations have been improved and the human errors have been eliminated.
System for thermal design on chip- and board-level of electronic components is introduced. It is integrated with Mentor Graphics CAD and consists of three subsystems: thermal design in IC Station; thermal design in Expedition PCB; thermal measurement for verification of temperature modeling results.
Automated electro-thermal analysis is realized in the last version of Mentor Graphics PCB Design System. The special software tool AETA is developed and integrated into the Expedition Enterprise PCB Design System to automate the process of power-temperature traffic between electrical and thermal simulators. Furthermore AETA provides the graphical user interface and the possibility to use the different versions of Mentor Graphics software.
The methodology and software tools for multi-level thermal and electro-thermal design of electronic components is presented. The discussion covers 2D/3D constructions of: 1) discrete and integrated semiconductor devices; 2) monolithic and hybrid ICs; 3) MCMs and PCBs. The actual test validation through thermal measurement is demonstrated for all types of components.
Hardware-software subsystem designed for MOSFETs characteristic measurement and SPICE model parameter extraction taking into account radiation effects is presented. Parts of the system are described. The macromodel approach is used to account for radiation effects in MOSFET modeling. Particularities of the account for radiation effects in MOSFETs within the measurement and model parameter extraction procedures are emphasized. Application of the subsystem is illustrated on the example of radiation hardened 0.25 μm SOI MOSFET test structures.