SystemC NoC Simulation as the Alternative to the HDL and High-level Modeling
Actual trends of networks-on-chip research and known approaches to their modeling are considered. The characteristics of analytic and high- / low- level simulation are given. The programming language SystemC as an alternative solution to create models of networks-on-chip is proposed, and SystemC models speed increase methodic is observed.
The article presents the concept of networks on chip (NoC) as a promising alternative to the communication subsystem for multiprocessor systems with bus architecture. Various approaches to modeling NoC are given and as the necessary software tools to evaluate NoC performance parameters the structure and simulation software solution for WFC-networks with virtual channels, XY-routing and various topologies are proposed. The testing of the simulator is performed by the example of the simulation of dependence of the average number of hops, needed for packets passing the network, from the dimension of NoC for mesh and torus topologies.
This paper proposes an approach to the synthesis and modeling of networks-on-chip (NoCs) by using the NoCSimp library based on a simplified wormhole router with central buffer and without virtual channels. The analysis of the results of simulation and synthesis of NoCs with regular and quasi-optimal topologies with number of nodes 8 and 9 is given. It is shown that in the case where the number of NoC nodes is not a power of 2 the use of quasi-optimal topologies offers a significant advantage.
The comparative analysis of different approaches to modeling of networks on chip (SoC) is provided in the article. The basic directions of exploratory research topics of SoC are defined and it is shown that modeling, analysis and simulation of SoC are basical to conduct other researches.
The typical approaches to modeling of the SoC and examples of their applications, advantages and disadvantages are characterized. They are: 1) analytical modeling (obvious approach, which does not require the use of special computer-aided design, but the analysis of such models is difficult because of their complexity and non-linearity behavior of SoC); 2) high‑level simulation (applicable to most destinations of SoC research, where there is no reference to the hardware implementation and it is necessary to get the quick simulation results with sufficient accuracy); 3) low-level HDL-modeling (it has a high accuracy, model adjustability and the possibility to synthesize the SoC, but requires a lot of time for the development of models and simulation).
The use of SystemC language for modeling SoC that enables to reduce defects and combine the advantages of low-level and high-level approaches is proposed. Modeling with SystemC is a universal approach applicable to all areas of exploratory research on the SoC.
This article gives a review of existing methods of designing of networks‑on‑chip (NoC), based on the approach that makes the projection of the characteristic task graph on a given regular topology. The general problem of NoC synthesis is characterized. The network topology can be either specialized and selected depending on the tasks to be performed or can be known in advance, in most cases, a regular topology. The method of NoC synthesis by adjusting for a specific task is analyzed. The advantages and disadvantages of this approach and the effect, achieved by its use for various implementations of NoCs are shown. The way to improve the NoC synthesis by using pre-defined irregular topologies with better characteristics is proposed.
The article gives a brief description of NoC simulator NoCTweak, based on SystemC. Mesh NoC simulation shows that the central location of "hot spots" allows up to 9% reduction in the delay of packets, up to 15.2% – in energy consumption for each packet transmission and up to 19.5% increase of the network capacity.
The article gives a review of existing methods of networks-on-chip design, based on the approach, in which the projection of the characteristic tasks graph is performed on a given regular topology. The general problem of the synthesis of networks-on-chip is characterized. The network topology can be foreknown (usually a regular topology) or selected in accordance with the tasks that will be performed by the network-on-chip. The first method of synthesis of networks-on-chip is widespread among the developers due to its relative simplicity and obviousness and presented in a variety of implementations, which are reviewed in this article. The advantages and disadvantages of this approach, the effect achieved by its application to various implementations of networks-on-chip and the way of its improvement, which is to extend the scope of solutions for regular network topologies on the predetermined irregular topologies with better characteristics are offered.