Electronic Computer-Aided Design for Low-Level Modeling of Networks-on-Chip

IEEE Access. 2024. Vol. 12. P. 48750–48763.

Lezhnev E., Zunin V., Amerikanov A., Romanov A.

This article proposes a Network-on-Chip (NoC) communication subsystem model on the basis of which the Electronic Computer-Aided Design (ECAD) architecture in the form of software is implemented. It makes it possible to automate the process of preparing and generating an HDL description of the NoC model in the Verilog language. It is shown that not in all cases it is required to model the entire NoC. Often, it is necessary to model its certain parts, such as a communication subsystem, routing algorithm, and traffic control system. The developed model allows modeling a parameterized NoC communication subsystem to obtain an estimate of the consumed logical blocks and registers required for prototyping the communication subsystem. All components of the communication subsystem are implemented as separate modules due to which the hardware costs for adding the necessary components for the study are reduced because of the absence of the need to completely rework the model program code every time. The effectiveness of using the developed ECAD and low-level modeling automation methods to study the work of routing algorithms for NoC topologies is demonstrated.

Keywords: modeling, HDL, network-on-chip (NoC), electronic computer-aided design (ECAD), RTL

Publication based on the results of: Automation of networks-on-chip modeling (2023)