Проблемы разработки перспективных микро- и наноэлектронных систем (МЭС-2018)
A set of modified compact spice models of field effect transistors is presented: with isolated gate (MOSFET) and with pn junction control (JFET) for circuit simulation in a temperature range of -200°C, which is important for space applications. All models are constructed using the approach combining macromodeling based on the standard models available in the library of spice models and introducing approximating dependencies for the temperature-dependent parameters of the model. For all models of the complex, a unified automated procedure for extraction of parameters has been worked out, providing an acceptable accuracy of electrical and temperature effects accounting for practical applications in the temperature range from room temperature to -200°C.
Using published MOSFETs characteristic degradation after TID irradiation in various thermal ambient parameters of “electro-thermo-rad” SPICE models were defined. Two examples were considered: radiation hardened 2 µm CMOS technology of Sandia National Laboratory and 130 nm CMOS technology. Models were verified using SRAM sell simulation (for 2 µm technology) and voltage reference, ring oscillator and logic gates circuit (for 130 nm technology). For the cases when elevated temperature leads to enhanced interface traps generation in MOSFET oxides, the paper presents quantitative estimates for the increased degradation of mentioned circuits characteristics under the mentioned external conditions. The importance of taking into account the combined temperature and total dose influence on CMOS circuit is shown.
Nowadays, construction of multi-core processors is becoming one of the most popular areas of investigation in computer science field; transition to multi-core processors allows overcoming the performance decrease, observed in complex single-core system design. Increase in core number, however, raise the issue of choosing the best topology, because classic topologies (mesh, hypercube, torus) fail to meet the requirements of modern networks with numerous cores. In this paper, multiplicative circulants, as a possible topology for networks-on-chip, are considered. Comparison of main characteristics of chosen type of circulants with characteristics of widely used mesh topology, makes it possible to consider multiplicative circulants to be a better topology for multi-core systems and to suggest the packet design for simple static routing technique based on classic breadth first search (BFS) algorithm. However, universal solutions have never been the best for a certain class of objects, so a specialized routing algorithm, taking into account the peculiarities of multiplicative circulants, was elaborated. By utilizing only mathematic operations, the developed algorithm managed to avoid exponential dependency on number of nodes inherent to BFS algorithm and demonstrated good performance even for networks with hundreds of nodes. Moreover, the presented algorithm required less service data in the packet, because only the target node number was needed for proper work.