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Test Program Generator MicroTESK for RISC-V
P. 6–11.
The paper presents a test program generator for functional verification of RISC-V microprocessors. The generator is implemented on the base of MicroTESK framework and consists of formal specifications of RISC-V ISA and ISA-independent core. The specifications describe instructions' syntax and semantics and can be easily modified to support more instructions (including custom extensions). The core implements techniques of instruction sequences composition and test data generation. Test programs are generated from test templates, describing the programs' structural and behavioral properties; among generation techniques, random, combinatorial, and constraint-based ones are supported.
In book
Austin: IEEE Computer Society, 2018.
Volkov V., Romanova I., , in: 2025 International Russian Automation Conference (RusAutoCon).: IEEE, 2025. P. 461–466.
Added: October 5, 2025
M. Y. Romashikhin, , in: 2025 International Russian Automation Conference (RusAutoCon).: IEEE, 2025. P. 225–230.
This paper discusses the application of networks-on-chip (NoCs) for solving DSP problems. NoC is a promising architecture for organizing multicore DSP systems due to scalability and parallel data transfer between IP-cores. Filtering was chosen as a task for signal processing in this work. A technique for partitioning the filtering task into multiple network nodes. An ...
Added: October 2, 2025
Смит С., М.: ДМК Пресс, 2025.
Данная книга продолжает серию «Книжная полка Истового инженера»,
которая издается при поддержке компании YADRO. Издание подготовлено к
публикации Московским институтом электроники и математики им. А. Н. Тихонова НИУ ВШЭ совместно с издательством «ДМК Пресс».
Перед вами переведенная и адаптированная для русскоязычного читателя книга С. Смита «RISC-V Assembly Language Programming», вышедшая
в издательстве Apress в серии Maker Innovations в 2024 ...
Added: May 25, 2025
Gorshkov A., Rumyantsev K., Yakovlev P., Working papers by Cornell University. Series math "arxiv.org" 2024
Handling vast amounts of data is crucial in today's world. The growth of high-performance computing has created a need for parallelization, particularly in the area of machine learning algorithms such as ANN (Approximate Nearest Neighbors). To improve the speed of these algorithms, it is important to optimize them for specific processor architectures. RISC-V (Reduced Instruction ...
Added: October 8, 2024
Markov D., Romanov A., , in: 2022 International Ural Conference on Electrical Power Engineering (UralCon).: IEEE, 2022. P. 180–184.
RISC-V is a new and rapidly developing instruction set architecture, the main feature of which is its openness for the free use. For this reason, RISC-V is becoming more and more popular among companies with a wide range of specializations, both with hardware and software developers. The RISC-V architecture specification defines a set of standard ...
Added: November 18, 2022
Tatarnikov A., Kamkin A., Проценко А. С. et al., Проблемы разработки перспективных микро- и наноэлектронных систем (МЭС) 2018 № 2 С. 2–8
In this paper, a specification-based test program generator for functional verification of RISC-V microprocessors is presented. The tool is based on the MicroTESK framework and consists of two main parts: (1) the formal specifications of the RISC-V ISA and (2) the ISA-independent generation core. Test programs are generated on the basis of the ISA specifications and test templates ...
Added: October 30, 2018
Kamkin A., Tatarnikov A., Смолов С. А. et al., , in: 2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV).: IEEE, 2015. P. 1–6.
In this paper, a tool for automatically generating test programs for ARM VMSAv8-64 memory management units is described. The solution is based on the MicroTESK framework being developed at ISP RAS. The tool consists of two parts: an architecture-independent test program generation core and VMSAv8-64 specifications. Such separation is not a new principle in the ...
Added: July 18, 2018
Kamkin A., Tatarnikov A., Проценко А. С. et al., , in: 2017 18th International Workshop on Microprocessor and SOC Test and Verification (MTV).: IEEE, 2017. P. 10–14.
The specification-based approach is widely used for test program generation for functional verification of microprocessors. The size of microprocessor specifications is measured in thousands lines of code. Consequently, their maintenance requires significant effort. Typical maintenance activities include regular updates, substitution of deprecated functionality, and support for new revisions and implementation-defined features. Our team is working ...
Added: July 18, 2018
Tatarnikov A., Kamkin A., Смолов С. А. et al., Программирование 2014 Т. 1 № 40 С. 3–14
Development of test programs and analysis of the results of their execution is the basic approach to verification of microprocessors at the system level. There is a variety of methods for the automation of test generation, starting with the generation of random code and ending with directed model-based test generation. However, there is no cure-all ...
Added: February 5, 2018
Tatarnikov A., Kamkin A., Чупилко М. М. et al., , in: Hardware and Software: Verification and Testing. HVC 2017. Lecture Notes in Computer ScienceVol. 10629: 13th International Haifa Verification Conference, HVC 2017, Haifa, Israel, November 13-15, 2017.: Cham: Springer, 2017. P. 217–220.
The paper presents MicroTESK, a tool that automates construction of test program generators for microprocessors. A constructed generator consists of the core that implements architecture-independent generation methods and the model that holds information required to generate tests for the corresponding architecture. The tool extracts this information from formal specifications of the instruction set architecture. The ...
Added: January 24, 2018
Tatarnikov A., Kamkin A., , in: Perspectives of System Informatics - 11th International Andrei P. Ershov Informatics Conference, PSI 2017, Moscow, Russia, June 27-29, 2017, Revised Selected Papers, Lecture Notes in Computer ScienceVol. 10742.: Springer, 2018. P. 387–393.
The paper presents MicroTESK, a tool for test program generation for functional verification of microprocessors. It generates test programs from templates which describe generation tasks in terms of constraints that must be satisfied in order to reach certain coverage goals. The tool uses formal specifications of the instruction set as a source of knowledge about ...
Added: January 23, 2018
Tatarnikov A., , in: Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2016).: Yerevan: IEEE, 2016. P. 270–273.
The paper proposes an approach to instruction stream generation for verification of microprocessor designs. The approach is based on using formal specifications of the instruction set architecture as a source of knowledge about the design under verification. This knowledge is processed with generic engines implementing an extensible set of generation strategies to produce stimuli in ...
Added: December 22, 2017
Tatarnikov A., Kamkin A., Сергеева Т. И. et al., , in: Proceedings of the 7th Spring/Summer Young Researchers’ Colloquium on Software Engineering, SYRCoSE 2013.: Kazan: -, 2013. P. 51–57 .
Creation of test programs and analysis of their
execution is the main approach to system-level verification of microprocessors. A lot of techniques have been proposed to automate test program generation, ranging from completely random to well directed ones. However, no “silver bullet” has been found. In good industrial practices, various methods are combined complementing each other. ...
Added: December 20, 2017
Tatarnikov A., Kamkin A., , in: Proceedings of the 6th Spring/Summer Young Researchers’ Colloquium on Software Engineering, SYRCoSE 2012.: Perm: -, 2012. P. 64–69.
Test program generation plays a major role in functional verification of microprocessors. Due to tremendous growth in complexity of modern designs and rigid constraints on time to market, it becomes an increasingly difficult task. In spite of powerful test program generators available in the market, development of functional tests is still known to be the ...
Added: December 13, 2017
Tatarnikov A., Проблемы разработки перспективных микро- и наноэлектронных систем (МЭС) 2016 Т. II С. 38–45
Test program generation and simulation is the most widely used approach to functional verification of microprocessors. Functional verification is a quite time consuming process. According to various estimates, it accounts for more than 70% of overall resources spent on designing a new microprocessor. This can be explained by the fact that modern hardware designs have ...
Added: December 12, 2017
Tatarnikov A., Kamkin A., Чупилко М. М. et al., Труды Института системного программирования РАН 2014 Т. 26 № 1 С. 149–200
Ensuring the correctness of microprocessors and other microelectronic equipment is a fundamental problem. To deal with it, various tools for functional verification are used. Unlike bugs in software programs which are relatively easy to fix (it does not apply to their consequences), defects in integrated circuits (both design and manufacturing ones) cannot be removed. In spite ...
Added: December 11, 2017
Tatarnikov A., Kamkin A., Проценко А. С., Proceedings of the Institute for System Programming of the RAS 2015 Vol. 27 No. 3 P. 125–138
A memory subsystem is one of the key components of a microprocessors. It consists of a number of storage devices (instruction buffers, address translation buffers, multilevel cache memory, main memory, and others) organized into a complex hierarchical structure. Huge state space of a memory subsystem makes its functional verification extremely labor consuming. Nowadays, the main ...
Added: December 10, 2017
Tatarnikov A., Proceedings of the Institute for System Programming of the RAS 2016 Vol. 28 No. 4 P. 77–98
Test program generation and simulation is the most widely used approach to functional verification of microprocessors. High complexity of modern hardware designs creates a demand for automated tools that are able to generate test programs covering non-trivial situations in microprocessor functioning. The majority of such tools use test program templates that describe scenarios to be ...
Added: November 26, 2017