Разработка HDL модели сети на кристалле на основе маршрутизатора с одной очередью
Various approaches to networks on chip organizing are considered. Тhe main drawback of networks on chip packet switching is identified – an excessively large buffers amounts of input and output buffers of routers. The new router architecture with improved resource consumption and high speed action is offered. Figs: 5. Ref.: 12 titles.
On the basis of an integrated network-on-chip (NoC) topologies optimality criterion, as well as applying the adjacency matrix to describe NoC topologies, exhaustive search method and its modification by using branch and bound and Monte Carlo methods are extended to the synthesis of NoC quasi-optimal topologies. Designed ScaNoC suboptimal topology synthesis algorithm is implemented on a high-level programming language which makes it possible to generate quasi-optimal topological solutions in accordance with the requirements to reduce hardware costs and the average distance between nodes. Proposed quasi-optimal topologies synthesis algorithm improvement by using the method of parallel computing allows speeding up the process of synthesis to 2117 times and getting topologies with the number of nodes up to 18.
The main approaches to the synthesis of networks-on-chip based on regular and specialized topologies are analyzed. The optimality criteria of the topologies of networks-on-chip and a new class of quasi-optimal topologies and methods for their synthesis are proposes. The requirements for quasi-optimal topologies are defined. By using the mathematical methods of optimization the analysis of the obtained quasi-optimal topologies for the number of nodes of 25 is performed. It is shown, that their properties are close to the theoretically possible optimal topologies to not less than 96.3%.
The article gives a brief description of NoC simulator NoCTweak, based on SystemC. Mesh NoC simulation shows that the central location of "hot spots" allows up to 9% reduction in the delay of packets, up to 15.2% – in energy consumption for each packet transmission and up to 19.5% increase of the network capacity.
The different approaches to the optimization of network communications subsystem on a chip are considered. The mesh and pseudo-optimal topologies with 8 and 9 nodes using System Verilog library Netmaker are modelled. It is shown, that mesh topologies of rectangular form are less efficient, than square ones; pseudo-optimal topologies have a higher threshold of saturation compared to the mesh and they have no restrictions on the number of nodes. Figs: 3. Ref.: 8 titles.