Proceedings of IEEE East-West Design & Test Symposium (EWDTS’13)
The main target of the IEEE East-West Design & Test Symposium (EWDTS-2013) is to exchange experiences between scientists and technologies of Eastern and Western Europe, as well as North America and other parts of the world, in the field of design, design automation and test of electronic circuits and systems. EWDTS’13 covers the following topics:
• Analog, Mixed-Signal and RF Test
• Analysis and Optimization
• EDA Tools for Design and Test
• Failure Analysis, Defect and Fault
• Modeling & Fault Simulation
• Power Issues in Testing
• Reliability of Digital Systems
• Thermal, Timing and Electrostatic Analysis of SoCs and Systems on Board
The temperature-current rise in modern (up to 100-150 microns wide) PCB traces is simulated using three software tools ANSYS, HyperLynxThermal and ELCUT. The results are compared with the IR measurements in PCB copper traces with different sizes and substrate materials. It is shown that ANSYS correctly describes the thermal behavior for all tests, other tools have some limitations for small size traces.
Single event upsets (SEU) produced by heavy ions in SOI CMOS SRAM cells were simulated using a mixed-mode approach, that is, two-dimensional semiconductor device simulation by TCAD tool coupled with circuit SPICE simulator. The effects of parasitic BJT and particle strike position on the SOI CMOS SRAM cells upset for transistor length scaling from 0.25 um to 65nm are presented.