Proceedings of XV IEEE East-West Design & Test Symposium (EWDTS'2017)
The main target of the East-West Design & Test Symposium (EWDTS) is to exchange experiences between the scientists and technologies of the Eastern and Western Europe, as well as North America and other parts of the world, in the field of design, design automation and test of electronic systems. The symposium aims at attracting scientists especially from countries around the Black Sea, the Baltic states and Central Asia. We cordially invite you to participate and submit your contribution(s) to EWDTS’16 which covers (but is not limited to) the following topics:
- Analog, Mixed-Signal and RF Test
- Analysis and Optimization
- ATPG and High-Level TPG
- Automotive Reliability & Test
- Built-In Self Test
- Debug and Diagnosis
- Defect/Fault Tolerance and Reliability
- Design Verification and Validation
- EDA Tools for Design and Test
- Embedded Software Performance
- Failure Analysis, Defect and Fault
- Functional Safely
- High-level Synthesis
- High-Performance Networks and Systems on a Chip
- Internet of Things Design & Test
- Low-power Design
- Memory and Processor Test
- Modeling & Fault Simulation
- Network-on-Chip Design & Test
- Modeling and Synthesis of Embedded Systems
- Object-Oriented System Specification and Design
- On-Line Testing
- Power Issues in Design & Test
- Real Time Embedded Systems
- Reliability of Digital Systems
- Scan-Based Techniques
- Self-Repair and Reconfigurable Architectures
- Signal and Information Processing in Radio and Communication Engineering
- System Level Modeling, Simulation & Test Generation
- System-in-Package and 3D Design & Test
- Using UML for Embedded System Specification
- Optical signals in communication and Information Processing
- CAD and EDA Tools, Methods and Algorithms
- Hardware Security and Design for Security
- Logic, Schematic and System Synthesis
- Place and Route
- Thermal and Electrostatic Analysis of SoCs
- Wireless and RFID Systems Synthesis
In this work features of measurement, processing and analysis of electrical characteristics of MOSFET’s subjected to various kinds of static irradiation (neutron, electron, and -rays) and temperature in the extended high/low ranges are analyzed. As a result a unified (with account for radiation and temperature) automated measurement, parameters extraction and modeling system is developed, which presents a unified environment for a user. Examples are given of the system usage for estimation of integrated and discrete power MOSFET radiation/temperature hardness and their SPICE model parameters extraction.
The combined Electro-Thermo-Rad models were developed for SPICE simulation of hardened SOI/SOS CMOS ICs for aero-space applications. They account for thermal (low, high temperature, selfheating) and radiation effects (total dose, particles fluence, single heavy particles, transient ionizing radiation effects) in SPICE model of MOSFET fabricated with SOI/SOS semiconductor technologies. The models were built using macromodeling approach, standard SPICE models for MOSFETs (BSIMSOI or EKV) and model parameters dependences on temperature and radiation factors. Combined account for radiation and thermal factors in SPICE model are described for the mentioned radiation factors. The main emphasis is on combined account for TID and temperature effects in the developed model. Some examples of the Electro-Thermo-Rad models application for combined simulation of radiation and thermal effects are presented.
On the basis of an integrated network-on-chip (NoC) topologies optimality criterion, as well as applying the adjacency matrix to describe NoC topologies, exhaustive search method and its modification by using branch and bound and Monte Carlo methods are extended to the synthesis of NoC quasi-optimal topologies. Designed ScaNoC suboptimal topology synthesis algorithm is implemented on a high-level programming language which makes it possible to generate quasi-optimal topological solutions in accordance with the requirements to reduce hardware costs and the average distance between nodes. Proposed quasi-optimal topologies synthesis algorithm improvement by using the method of parallel computing allows speeding up the process of synthesis to 2117 times and getting topologies with the number of nodes up to 18.
The parameter optimization features of CMOS operational amplifiers (OA) based on dual-input-stage under constraints on power consumption, unity gain frequency, phase margin, open loop gain and compensation capacitance are considered. It is shown that the maximum slew rate of the output voltage is proportional to the DC currents of dual-input-stage due to the usage of current mirror based push-pull parallel channels. The recommendations to design of high-speed CMOS OA with wide range of dynamic characteristics are given
The paper presents SPICE models of nonlinear capacitors for analysis of ferroelectric circuits. The capacitors can be defined by either charge-voltage or voltage-charge closed form expressions. Additionally the model for series connection of any number of nonlinear capacitors is proposed. The model takes into account trapped charges of internal connections. Numerical experiments for ferroelectric circuits confirmed the correctness of the proposed approach.
Stochastic Local Search (SLS) is one of the most popular approaches to Boolean satisfiability problem and solvers based on this algorithm have made a substantial progress over the years. However, nearly all state of the art SLS solvers do not attempt to find a good starting point, instead using random values. We present a heuristic for finding an initial assignment based on non-linear optimization of continuous extension of given Boolean formula. This heuristic works by optimizing continuous function that represents the formula and then converting the result into discrete values. We also provide experimental evaluation of new heuristic implemented in ProbSAT solver.
The secular outcome of our investigation is development of new monitoring service for glucose control related to diabetes. It is based on the main results of research: 1) New innovative wearable sensor that carry non-invasive measurement of glucose level. Sensor uses several independent technologies, simultaneously: radio-frequency with different levels of signal, ultrasonic, electromagnetic and thermal; 2) Special mobile application as the principal interface monitor for personal usage; 3) The unique proprietary algorithm, based on neural net, which calculates the weighted average and returns the user's glucose level. The algorithm précises the results of measurements, based on genetic neural net ideas; 4) Special designed Data Base Storage in our cloud software specialized for gathering information and giving the predictions for patient. All results together makes the essence of the research.