Compact Si JFET Model for Cryogenic Temperature
Compact Si JFET model for SPICE circuit simulation in the extended temperature range from 373 K down to 73 K (+100 °C…−200 °C) is proposed. It is based on the standard JFET model Level = 3 (Statz model) with the full set of temperature-dependent parameters in the cryogenic temperature range. The universal procedure for model parameter extraction from I-V-characteristic measurement data at low temperature is developed. The simulation error does not exceed 10–15% in the temperature range 373 K…73 K. The JFET Low-T model is implemented in the form of a subcircuit and tested in popular SPICE-like circuit simulators: HSPICE, LTSpice, ADS, and OrCAD.