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Regular version of the site

Article

TCAD Simulation of Dose Radiation Effects in Sub-100 nm High-k MOSFET Structures

Russian Microelectronics. 2018. Vol. 47. No. 7. P. 487-493.

The sub-100-nm CMOS process with a high-κ gate dielectric is one of the key technologies for the
fabrication of digital, analog, and RF VLSI circuits and on-chip systems. The influence of ionizing radiation
on 45-nm MOS transistors with a high-κ dielectric fabricated using the bulk-silicon and SOI technologies is
simulated. Effects induced by the substitution of SiO2 with a high-κ dielectric are noted. The processes of
selection and tuning of physical models for the simulation of high-κ MOS transistors in the Sentaurus TCAD
are outlined. A set of new physical semiempirical models introducing the dependence of radiation-sensitive
parameters (carrier lifetime, carrier mobility, charge density in the bulk of SiO2 and HfO2 and at the HfO2/Si
interfaces) on the irradiation dose is developed. Nanoscale bulk and SOI MOS transistors with a high-κ
dielectric are simulated. It is demonstrated that an increase in the drain current after irradiation in nanoscale
SOI structures is induced by the charge accumulation in the side oxide. An acceptable fit between the simulation
results and the experimental data is obtained. The simulation results confirm that the leakage current
is suppressed (compared to common MOS transistors with SiO2) in sub-100-nm MOS transistors with a
high-κ dielectric. However, the other important parameters of sub-100-nm MOS transistors with a high-κ
dielectric are more sensitive to ionizing radiation.