The dependence of the thermal characteristics of TVS-diodes during the passage of the pulse overload has been studied. The time dependences of the pulse voltage limitation and current are analyzed. Based on the analysis of the dependences, the thermal characteristics of the TVS-diode are calculated. It is shown that the parameters of the TVS-diodes deteriorate on reaching a current density of 160–300 A/cm2 and critical temperature of 250–300°С. The dependences of the thermal resistance and critical temperature of the TVS-diodes on the current density and the pulse duration are presented.
The monitoring methods for measuring the film structure parameters in formation process, namely, the in situ methods, are currently of special significance. Their application provides obtaining the films with the given characteristics, which results in a fast correction of the technological modes. The possibilities of the in situ method of the X-ray reflectometry for defining the parameters of the nanodimensional films during their formation are discussed. The results are given of testing the magnetron deposition of the silicon films and other materials on the silicon substrate.
The influence of the topological parameters of shunts in the cathode regions of a photothyristor on the dV/dt effect is calculated. The analytical condition that makes it possible to determine, in the first approximation, the region of the onset of the structure triggering caused by the dV/dt effect is obtained. When the forward voltage increases on the thyristor structure in the off state, the bias current flowing through the barrier capacitance of the inversely biased p-base-n-base junction causes a spontaneous triggering of the structure. This is the core of the dV/dt effect in thyristors
The mechanisms of the formation of the peak value of the electronic component of the total cur rent through a BISPINdevice in various modes of pulsation are considered. The results of the experimental and theoretical studies of the electronic component of the current through the structure on the supply voltage and load resistance are given. A theoretical model to explain the observed dependence is proposed. A good agreement between the calculated and experimental results is obtained.
The factors affecting the thermal degradation of a single silicon field-emission pointed cathode during the take-off of the emission current are described experimentally. The results of the numerical modeling of the temperature dynamics of the field-emission cathode in conditions of the presence of a free interface between the liquid and solid phases allowing for the surface tension are described.
The theory of dispersion of surface plasma waves in semiconductor nanotubes is presented. The effect of screening the Coulomb field of static point charge by magnetized electron gas of nanotube is investigated. The main properties of the semiconductor nanotube plasma, 3D plasma, and planar 2D plasma are compared. The dependences of critical temperature and thermodynamic properties of superconducting quantum cylinder on the characteristics of the system are studied.
SOI MOSFETs have the worst properties of heat removal from an active region, which negatively affects the reliability and efficiency of integrated circuits. Using TCAD modeling, we investigate the self-heating effect in the following structures of deeply submicron MOSFETs with different configurations of buried oxide: traditional bulk MOSFET, SOI structure, SELBOX structure, partial SOI structure, thin-BOX SOI structure, UTBB SOI structure, and quasi-SOI structure. It is shown that, for a number of new designs, the maximum temperature in the MOSFET structure is significantly reduced as compared to Тmax of the standard SOI MOSFET structure; it approaches the values typical of standard MOSFETs on bulk silicon.
A compact BSIMSOI-RAD macromodel for SOI/SOS CMOS transistors is developed that takes into account the radiation effects. An automated procedure for determination of macromodel parameters is described and shown to be useful for analyzing radiation hardness of CMOS IC fragments depending on the total absorbed dose. The simulation time is estimated.
The models of electrophysical effects built-into Sentaurus TCAD have been tested. The models providing an adequate modeling of deep submicron high-k MOSFETs have been selected. The gate and drain leakage currents for 45 nm MOSFETs with polysilicon gate oxide and SiO2, SiO2/HfO2 and HfO2 gate dielectrics have been calculated using TCAD. It has been shown that the replacement of the traditional SiO2 gate by an equivalent HfO2 dielectric reduces the gate leakage current by several orders of magnitude due to the elimination of the impact of the tunneling effect. Besides, the threshold voltage, saturation drain current, mobility, transconductance, etc., degrade within a range of 10–20%.
The sub-100-nm CMOS process with a high-κ gate dielectric is one of the key technologies for the fabrication of digital, analog, and RF VLSI circuits and on-chip systems. The influence of ionizing radiation on 45-nm MOS transistors with a high-κ dielectric fabricated using the bulk-silicon and SOI technologies is simulated. Effects induced by the substitution of SiO2 with a high-κ dielectric are noted. The processes of selection and tuning of physical models for the simulation of high-κ MOS transistors in the Sentaurus TCAD are outlined. A set of new physical semiempirical models introducing the dependence of radiation-sensitive parameters (carrier lifetime, carrier mobility, charge density in the bulk of SiO2 and HfO2 and at the HfO2/Si interfaces) on the irradiation dose is developed. Nanoscale bulk and SOI MOS transistors with a high-κ dielectric are simulated. It is demonstrated that an increase in the drain current after irradiation in nanoscale SOI structures is induced by the charge accumulation in the side oxide. An acceptable fit between the simulation results and the experimental data is obtained. The simulation results confirm that the leakage current is suppressed (compared to common MOS transistors with SiO2) in sub-100-nm MOS transistors with a high-κ dielectric. However, the other important parameters of sub-100-nm MOS transistors with a high-κ dielectric are more sensitive to ionizing radiation.
The compact models of junction field effect transistors (JFETs) used in release-quality versions of SPICE-like programs are focused only on the standard temperatures ranging from –60 to 150°C and are unworkable for an electronic circuit design in the cryogenic temperature range (below –120°C). It this study, the Low-T SPICE model of the JFET for designing electronic circuits in the extended temperature range, including the cryogenic range (from –200 to 110°С), is proposed. The model takes into account the changes in the I–V curves caused by the effect of ultralow temperature: growth of the saturation voltage VD sat, decrease of the pinch-off current Ip and steepness BETA, negative slope LAMBDA of the output I–V curves, increase of the drain–source resistance RD as the result of the freezing effect, etc. For this purpose, the dependences of the specified parameters on temperature are introduced in the model. The procedure for extracting the SPICE parameters of the Low-T SPICE model of the JFET is developed according to the results of the measurements of the standard set of the I–V curves in the cryogenic temperature range. The error of the calculation of the I–V curves is not higher than 10–15% in the temperature range from –200 to 110°C.