РАСЧЕТ ЗАДЕРЖЕК И ПОТЕРЬ НАПРЯЖЕНИЯ В МЕЖСОЕДИНЕНИЯХ БИС С ПОМОЩЬЮ КОМПАКТНОЙ ЭЛЕКТРО-ТЕПЛОВОЙ SPICE-МОДЕЛИ
General purpose of this work is development of program tools for delay modeling in LSI interconnections with account for thermal effects. Authors use the interconnection model in the form of distributed RC-circuit, which parameters depends on the chip surface temperature distribution. The chip surface temperature is calculated by program tool “Overheat-MC”. Interconnection model parameters – resistances and capacitances of RC circuit sections, are calculated on the basis of temperature distribution along the interconnection. This approach allows to take into account the influence of chip non-uniform overheat on interconnection electrical characteristics. For the simplification of interconnection model and CPU time decreasing the multi-sectional RC - model reduced to compact Pi-shaped equivalent circuit with temperature-depended parameters. It is shown that in conversion to Pi-shaped circuit, the signal magnitude error is at most 7%, the signal phase error is 2%. In this case CPU time decreases on 25-30%.