Ресурсоэффективный роутер для многопроцессорной сети на чипе
Various approaches to networks on chip organizing are considered. Тhe main drawback of networks on chip packet switching is identified – an excessively large buffers amounts of input and output buffers of routers. The new router architecture with improved resource consumption and high speed action is offered. Figs: 5. Ref.: 12 titles.