Обґрунтування вибору методу та засобів моделювання мереж на кристалі
The comparative analysis of different approaches to modeling of networks on chip (SoC) is provided in the article. The basic directions of exploratory research topics of SoC are defined and it is shown that modeling, analysis and simulation of SoC are basical to conduct other researches.
The typical approaches to modeling of the SoC and examples of their applications, advantages and disadvantages are characterized. They are: 1) analytical modeling (obvious approach, which does not require the use of special computer-aided design, but the analysis of such models is difficult because of their complexity and non-linearity behavior of SoC); 2) high‑level simulation (applicable to most destinations of SoC research, where there is no reference to the hardware implementation and it is necessary to get the quick simulation results with sufficient accuracy); 3) low-level HDL-modeling (it has a high accuracy, model adjustability and the possibility to synthesize the SoC, but requires a lot of time for the development of models and simulation).
The use of SystemC language for modeling SoC that enables to reduce defects and combine the advantages of low-level and high-level approaches is proposed. Modeling with SystemC is a universal approach applicable to all areas of exploratory research on the SoC.