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Компьютерное моделирование воздействия электростатических разрядов на мощные МОП транзисторы с учетом влияния емкости печатной платы

Константинов Ю. А., Горланов Е. С., Пожидаев Е. Д., Тумковский С. Р.

Computer simulation for the impact of electrostatic discharges (ESD) on the power IRF series MOS transistors have been carried out. The influence of the printed circuit board (PCB) capacitance values on the transistor gate-source voltage is investigated. This influence is significant for transistors with low gate – source capacitance was found.

The relation between the ESD voltage and capacitance, from which occurs breakdown of the gate oxide is found. It is shown that the power MOS transistors with the gate – source low capacitance should be ESD protected using a TVS diodes.