Control current stress technique for the investigation of gate dielectrics of MIS devices
In this study, a modified technique of control current stress to investigation thin gate dielectric of MIS structures is proposed. This technique allows to monitor charge trapping in gate dielectric of MIS structures under high-field and another stress situations (irradiation, plasma, hot carriers, etc.). The technique also may be used for testing thin gate dielectric defects. Unlike simple techniques, for example constant current stress and J-ramp current stress, the proposed method uses a sequence of stress current and measuring current pulses. At the same time, the processes of charging and discharging of the MIS structure capacitance as well as the charge trapping in the gate dielectric are taken into account. Charging of MIS structure from inversion to accumulation modes or back way allows one to retrieve a low frequency capacitive-voltage characteristic. Account charging capacitance of MIS structure and charge trapping in gate dielectric at injective mode lets considerably increase metrological characteristics of this technique and reduce inaccuracies. The models describing the change in the charge state of MIS structures, both in the charge capacity, and in the mode of injection of charge carriers were developed. Using these models let to choose optimal algorithm of current stress and increase measurement accuracy.