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Paley graphs and Cartesian product for designing promising topologies for networks-on-chip
The main goal of this work is to study promising network-on-chip topologies. Classical network-on-chip topologies, for example, mesh, ring torus, are well studied, but their configuration parameters are not the best among all existing ones. In this study, we study circulant topologies and their modifications, as well as evaluate their parameters in the context of designing networks on a chip (NoC). Recently, in a number of works [1,2], a proposal has appeared to use circulant topologies for designing NoC. The use of a new topology, which has better parameters of the diameter and average distance in comparison with the classical regular topologies (mesh, torus, ring), has made it possible to significantly advance in solving the problem of finding "optimal" topological structures. At the same time, the use of circulant topologies also has a number of disadvantages associated with the need to find optimal routing algorithms and combat the phenomenon of deadlocks and livelocks in the network. There is also a problem of finding families of optimal circulant graphs for the number of nodes more than 100 and the degree of vertices greater than 4 [3]. Thus, as the experience of previous studies has shown, a topological approach to improving the final characteristics of NoC by using more efficient topologies gives good results, and it should be developed by looking for new topologies that can be used in NoC.