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Of all publications in the section: 2
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Article
Shcherbatenko M., Lobanov Y., Semenov A. et al. Proceedings of SPIE. 2017. Vol. 10229. P. 102290G-1-102290G-12.

Achievement of the ultimate sensitivity along with a high spectral resolution is one of the frequently addressed problems, as the complication of the applied and fundamental scientific tasks being explored is growing up gradually. In our work, we have investigated performance of a superconducting nanowire photon-counting detector operating in the coherent mode for detection of weak signals at the telecommunication wavelength. Quantum-noise limited sensitivity of the detector was ensured by the nature of the photon-counting detection and restricted by the quantum efficiency of the detector only. Spectral resolution given by the heterodyne technique and was defined by the linewidth and stability of the Local Oscillator (LO). Response bandwidth was found to coincide with the detector's pulse width, which, in turn, could be controlled by the nanowire length. In addition, the system noise bandwidth was shown to be governed by the electronics/lab equipment, and the detector noise bandwidth is predicted to depend on its jitter. As have been demonstrated, a very small amount of the LO power (of the order of a few picowatts down to hundreds of femtowatts) was required for sufficient detection of the test signal, and eventual optimization could lead to further reduction of the LO power required, which would perfectly suit for the foreseen development of receiver matrices and the need for detection of ultra-low signals at a level of less-than-one-photon per second.

Added: Oct 13, 2017
Article
K. Petrosyants, E. Orekhov, I. Kharitonov et al. Proceedings of SPIE. 2012. Vol. 8700. P. 16.1-16.6.

In this paper we performed 2D and 3D device simulations to analyze the impact of technology scaling on the lattice heating in n-channel bulk silicon and silicon-on-insulator MOS transistors with gate lengths from 0.5 to 0.1 um. Maximum lattice temperatures and transistor thermal resistances for different gate lengths and bias voltages were calculated. The increase in device temperature and thermal resistance with transistor scaling was shown.

Added: Jan 23, 2014