Построение тестов цифровых схем с использованием обобщенной модели неисправностей и непрерывного подхода к моделированию
This paper considers the development of digital circuit tests using continuous models of discrete devices. An algorithm is presented which makes it possible to solve the problem of finding test sets using continuous optimization. A generalized fault model is proposed which implements a unified approach to the representation of different types of faults in test generation. The proposed approach is implemented as a software environment for research and development of fault models and algorithms for finding digital circuit tests. For testing, a system of automated test generation for constant faults of combinational circuits has been built. The performance estimation results for the software package developed for the ISCAS '85 benchmark circuits demonstrate the effectiveness of the algorithms and methods used.
Computationally constrained devices are devices with typically low resources / computational power built for specific tasks. At the same time, recent advances in machine learning, e.g., deep learning or hierarchical or cascade compositions of machines, that allow to accurately predict / classify some values of interest such as quality, trust, etc., require high computational power. Often, such complicated machine learning configurations are possible due to advances in processing units, e.g., Graphical Processing Units (GPUs). Computationally constrained devices can also benefit from such advances and an immediate question arises: how? This paper is devoted to reply the stated question. Our approach proposes to use scalable representations of ‘trained’ models through the synthesis of logic circuits. Furthermore, we showcase how a cascade machine learning composition can be achieved by using ‘traditional’ digital electronic devices. To validate our approach, we present a set of prelimin (More)
There have been many reports on advances in the development of learner corpora that have made it possible to effectively use these collections of texts for the benefit of the learning process. This paper lists all possible applications in English courses taught to Bachelor students of a middle-size learner corpus REALEC, which comprises student written works supplied with expert annotation of mistakes, browsing and search options, and some optional automated tagging system. Annotation in the corpus is given by either experts (mostly, EFL instructors), or by learners themselves under the supervision of their EFL instructors. As the first point, the paper argues that when EFL methodology requires that students apply the error classification in the process of annotating their peers’ essays and gradually their own essays as well, their understanding of subtle areas of grammar, vocabulary and discourse improves, and correspondingly, the number of errors in their written works decreases. The second argument concerns the tool for the development of placement and progress tests, which makes use of sentences with mistakes made by other learners – contributors to the corpus. In the suggested design of the tests sentences are automatically extracted from the same corpus, manually divided into three echelons according to the complexity of the change required in the correction of the mistake, and then administered to learners as a way of automated measurement of their proficiency in English. The submitted test is scored automatically within minutes. The third possibility considered in the research is the possibility to supplement the corpus with the platform of trainers automatically or semi-automatically set up on the basis of frequently marked errors made by a particular group of students. In conclusion we point out the ease and usefulness of the proposed applications both for EFL instructors and English learners.
This paper presents a novel rodent avoidance test. We have developed a specialized device and procedures that expand the possibilities for exploration of the processes of learning and memory in a psychophysiological experiment. The device consists of a current stimulating electrode-platform and custom software that allows to control and record real-time experimental protocols as well as reconstructs animal movement paths. The device can be used to carry out typical footshock-avoidance tests, such as passive, active, modified active and pedal-press avoidance tasks. It can also be utilized in the studies of prosocial behavior, including cooperation, competition, emotional contagion and empathy. This novel footshock-avoidance test procedure allows flexible currentstimulating settings. In our work, we have used slow-rising current. A test animal can choose between the current rise and time-out intervals as a signal for action in footshock avoidable tasks. This represents a choice between escape and avoidance. This method can be used to explore individual differences in decisionmaking and choice of avoidance strategies. It has been shown previously that a behavioral act, for example, pedal-pressing is ensured by motivation-dependent brain activity (avoidance or approach). We have created an experimental design based on tasks of instrumental learning: pedal-pressing in an operant box results in a reward, which is either a piece of food in a feeder (food-acquisition behavior) or an escape-platform (footshock-avoidance behavior). Data recording and analysis were performed using custom software, the open source Accord.NET Framework was used for real-time object detection and tracking.
The methodology of modeling and simulation of environmentally induced faults in radiation hardened SOI/SOS CMOS IC’s is presented. It is realized at three levels: CMOS devices – typical analog or digital circuit fragments – complete IC’s. For this purpose, a universal compact SOI/SOS MOSFET model for SPICE simulation software with account for TID, dose rate and single event effects is developed. The model parameters extraction procedure is described in great depth taking into consideration radiation effects and peculiarities of novel radiation-hardened (RH) SOI/SOS MOS structures. Examples of radiation-induced fault simulation in analog and digital SOI/SOS CMOS LSI’s are presented for different types of radiation influence. The simulation results show the difference with experimental data not larger than 10‒20% for all types of radiation.