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О «совершенствовании» математической модели расчета надёжности КМОП СБИС с учетом ЭСР

The considered model of the failure rate of CMOS VHSIC design proposed in the article Piskun G.A., Alekseev V.F., "Improvement of mathematical models calculating of CMOS VLSIC taking into account features of impact of electrostatic discharge", published in the first issue of the journal "Technologies of electromagnetic compatibility" for the year 2016. It is shown that the authors claim that this model "...will more accurately assess the reliability of CMOS VHSIC design" is fundamentally flawed and its application will inevitably lead to inadequate results. Alternatively, the proposed model of the failure rate of CMOS VHSIC design, which also allows to take into account the views of ESD, but based on the use of resistance characteristics of CMOS VHSIC to the effects of ESD.