Simulation of the Super-scalar Processor Core Operation
Abstract. The article considers the features of super-scalar processors, their way of performing several operations on several pairs of operands simultaneously. The research focuses on the organization of processor pipeline execution operation of several machine instructions in one processor core. The simulating kit was developed for better understanding of a processor core microarchitecture. It includes two parts: program and methodical recommendations with multiple task options. The simulating kit demonstrates the pipeline architecture consisting of two clusters: front-end and back-end and the principle of translating complex multi-cycle CISC-like instructions into simpler RISC-like micro-operations. The main types of machine instructions are considered: data transfer between registers and memory cells (four variations), data processing of couple of operands from registers and memory cells (four variations), conditional jump to the specified address. The program-simulator makes it possible to conduct a more detailed simulation of one of the three mechanisms for calculations accelerating in the processor core: multi-functional (super-scalar) processing, out-of-order processing, speculative instructions execution after the branch prediction. The simulating kit is used in educational process when training masters of Higher School of Economics National Research University.
Modern desktop processors are super-scalar, that is, they are able to perform several operations on several pairs of operands simultaneously. This is achieved by many ways of parallelizing calculations. The main method is the conveyor processing of machine instructions. Each processor contains from one to several cores. Each core contains one to several instruction pipelines. In fact, the pipeline is the heart of the processor. Understanding the mechanism of its work gives an understanding of the principles of computing in modern computers. A huge number of scientific and practical works are devoted to this issue, but a faster and more visual way to study the principle of conveyor processing is the launch and study of the simulation model of the processor core. In this paper we have built and investigated such a model that allows us to trace the process of executing machine instructions by the processor core pipeline. As a basis for the modeling are taken Intel processor with microarchitecture Nehalem, although the analyzed mechanisms inherent to other modern processors. Modeling system includes the program and methodical recommendations on its use with multiple task options. The computer model considers as an initial data a fragment of machine code on a simplified Assembler. The fragment consists of twenty instructions. Three main types of machine instructions are considered: data transfer between registers and memory cells (four variations), data processing from registers and memory cells (four variations), conditional jump to the specified address. The simulation program automatically generates a new version of the code fragment at startup or at the user's request. To study the principles of the pipeline, it is additionally proposed to specify the following parameters of the pipeline and the code: the number of store/load devices, the number of ALU (Executive devices), the percentage of memory operations. The modeling kit demonstrates the pipeline architecture consisting of two clusters: front-end and back-end and the principle of translating complex multi-cycle CISC-like instructions into simpler RISC-like micro operations (mops). In addition, it is possible to conduct a more detailed simulation of one of the three mechanisms for calculations accelerating in the processor core: multi-functional processing, out-of-order processing, speculative instructions execution after the branch prediction. The program includes four Windows of the model, which reflects the input parameters and simulation results. As a result of the simulation program provides the following options: x to explore the principle of translation of instructions in micro-operation ("MOPs" window), x to study the employment cycles of the main back-end pipiline cluster when executing the given instructions (the "Pipeline" window»), x to examine the time diagram of instructions execution from a given code fragment ("Diagram" window). This modeling kit is useful for studying computer architecture. Understanding the features of the processor is useful for both system developers and programmers. Improving the style of writing programs will speed up their execution by the computer.
A model for organizing cargo transportation between two node stations connected by a railway line which contains a certain number of intermediate stations is considered. The movement of cargo is in one direction. Such a situation may occur, for example, if one of the node stations is located in a region which produce raw material for manufacturing industry located in another region, and there is another node station. The organization of freight traﬃc is performed by means of a number of technologies. These technologies determine the rules for taking on cargo at the initial node station, the rules of interaction between neighboring stations, as well as the rule of distribution of cargo to the ﬁnal node stations. The process of cargo transportation is followed by the set rule of control. For such a model, one must determine possible modes of cargo transportation and describe their properties. This model is described by a ﬁnite-dimensional system of diﬀerential equations with nonlocal linear restrictions. The class of the solution satisfying nonlocal linear restrictions is extremely narrow. It results in the need for the “correct” extension of solutions of a system of diﬀerential equations to a class of quasi-solutions having the distinctive feature of gaps in a countable number of points. It was possible numerically using the Runge–Kutta method of the fourth order to build these quasi-solutions and determine their rate of growth. Let us note that in the technical plan the main complexity consisted in obtaining quasi-solutions satisfying the nonlocal linear restrictions. Furthermore, we investigated the dependence of quasi-solutions and, in particular, sizes of gaps (jumps) of solutions on a number of parameters of the model characterizing a rule of control, technologies for transportation of cargo and intensity of giving of cargo on a node station.
Event logs collected by modern information and technical systems usually contain enough data for automated process models discovery. A variety of algorithms was developed for process models discovery, conformance checking, log to model alignment, comparison of process models, etc., nevertheless a quick analysis of ad-hoc selected parts of a journal still have not get a full-fledged implementation. This paper describes an ROLAP-based method of multidimensional event logs storage for process mining. The result of the analysis of the journal is visualized as directed graph representing the union of all possible event sequences, ranked by their occurrence probability. Our implementation allows the analyst to discover process models for sublogs defined by ad-hoc selection of criteria and value of occurrence probability
The geographic information system (GIS) is based on the first and only Russian Imperial Census of 1897 and the First All-Union Census of the Soviet Union of 1926. The GIS features vector data (shapefiles) of allprovinces of the two states. For the 1897 census, there is information about linguistic, religious, and social estate groups. The part based on the 1926 census features nationality. Both shapefiles include information on gender, rural and urban population. The GIS allows for producing any necessary maps for individual studies of the period which require the administrative boundaries and demographic information.
It is well-known that the class of sets that can be computed by polynomial size circuits is equal to the class of sets that are polynomial time reducible to a sparse set. It is widely believed, but unfortunately up to now unproven, that there are sets in EXPNP, or even in EXP that are not computable by polynomial size circuits and hence are not reducible to a sparse set. In this paper we study this question in a more restricted setting: what is the computational complexity of sparse sets that are selfreducible? It follows from earlier work of Lozano and Torán (in: Mathematical systems theory, 1991) that EXPNP does not have sparse selfreducible hard sets. We define a natural version of selfreduction, tree-selfreducibility, and show that NEXP does not have sparse tree-selfreducible hard sets. We also construct an oracle relative to which all of EXP is reducible to a sparse tree-selfreducible set. These lower bounds are corollaries of more general results about the computational complexity of sparse sets that are selfreducible, and can be interpreted as super-polynomial circuit lower bounds for NEXP.
Many electronic devices operate in a cyclic mode. This should be considered when forecastingreliability indicators at the design stage.The accuracy of the prediction and the planning for the event to ensure reliability depends on correctness of valuation and accounting greatest possiblenumber of factors. That in turn will affect the overall progress of the design and, in the end,result in the quality and competitiveness of products
Let G be a semisimple algebraic group whose decomposition into the product of simple components does not contain simple groups of type A, and P⊆G be a parabolic subgroup. Extending the results of Popov , we enumerate all triples (G, P, n) such that (a) there exists an open G-orbit on the multiple flag variety G/P × G/P × . . . × G/P (n factors), (b) the number of G-orbits on the multiple flag variety is finite.
I give the explicit formula for the (set-theoretical) system of Resultants of m+1 homogeneous polynomials in n+1 variables