The brochure provides an overview of methodological and practical aspects of Russian scientific organisations and universities' participation in international science and technology (S&T) cooperation. The methodological manual offers a systematized approach to conducting international collaboration and contains reference information on S&T potenatial and S&T cooperation programmes of selected foreign countries.
The research leading to these results has received funding from the Ministry of Education and Science of the Russian Federation in the framework of the project “Development of Instruments for Methodological, Information and Analytical Support of Russia’s Scientific Organizations and Universities’ Participation in International Science and Technology Cooperation” (Subsidy Agreement no 14.602.21.0013 dated August 3, 2016 with the Russian Ministry of Education and Science in the framework of the federal targeted programme “Research and Development in Russian Priority S&T Development Areas in 2014–2020”, unique identification number – RFMEFI60216X0013).
This manual is aimed at consolidating the theoretical material on the section "Computer Architecture", "Cache memory". The manual provides information about the Cache memory subsystem architecture in a multiprocessor/multi-core computer, system memory and Cache memory appointment, the description of the maintain protocols of cache memory coherency, we considered a model of operation of a subsystem of the Cache memory in a multiprocessor/multi-core system using the maintain of cache memory coherency, implemented by using different protocols: MSI, MESI, MOSI, MOESI/MESIF.
The purpose of this manual is to consolidate the theoretical knowledge in areas of "computer microarchitecture", "CPU", "CISC-to-RISC pipelines". In this manual describes the features of the organization of the work of contemporary superscalar processors, the Intel architecture when running native commands. At the end of the laboratory work the student must have an understanding of the cycle and phases of operation of the processor core for execution of the command, the micro-operations and the number of them for different phases of the command. The student should be able to explain the graphs and tables the results of modeling for their version of the task and answer the questions placed at the end of this study guide.